Intel GD82559ER manual PCI Command Register PCI Command Register Bits

GD82559ER — Networkin g Silicon

7.1.2PCI Command Register

The 82559ER Command register at word address 04h in the PCI configuration space provides control over the 82559ER’s ability to generate and respond to PCI cycles. If a 0His written to this register, the 82559ER is logically disconnected from the PCI bus for all accesses except configuration accesses. The format of this register is shown in the figure below.

15 10 9 8 7 6 5 4 3 2 1 0

Reserved

0

0

0

0

SERR# Enable

Parity Error Response

Memory Write and Invalidate Enable

Bus Master Enable

Memory Space

IO space

Figure 18. PCI Command Register

Note that bits three, five, seven, and nine are set to 0b. The table below describes the bits of the PCI Command register.

		Table 5. PCI Command Register Bits
Bits	Name	Description
15:10	Reserved	These bits are reserved and should be set to 000000b.
		This bit controls a device’s ability to enable the SERR# driver. A value of 0b
8	SERR# Enable	disables the SERR# driver. A value of 1b enables the SERR# driver. This
		bit must be set to report address parity errors. In the 82559ER, this bit is
		configurable and has a default value of 0b.
		This bit controls a device’s response to parity errors. A value of 0b causes
		the device to ignore any parity errors that it detects and continue normal
6	Parity Error Control	operation. A value of 1b causes the device to take normal action when a
		parity error is detected. This bit must be set to 0b after RST# is asserted. In
		the 82559ER, this bit is configurable and has a default value of 0b.
		This bit controls a device’s ability to use the Memory Write and Invalidate
	Memory Write and	command. A value of 0b disables the device from using the Memory Write
4		and Invalidate Enable command. A value of 1b enables the device to use
	Invalidate Enable
		the Memory Write and Invalidate command. In the 82559ER, this bit is
		configurable and has a default value of 0b.
		This bit controls a device’s ability to act as a master on the PCI bus. A
2	Bus Master	value of 0b disables the device from generating PCI accesses. A value of
		1b allows the device to behave as a bus master. In the 82559ER, this bit is
		configurable and has a default value of 0b.
		This bit controls a device’s response to the memory space accesses. A
1	Memory Space	value of 0b disables the device response. A value of 1b allows the device
		to respond to memory space accesses. In the 82559ER, this bit is
		configurable and its default value of 0b.
		This bit controls a device’s response to the I/O space accesses. A value of
0	I/O Space	0b disables the device response. A value of 1b allows the device to
		respond to I/O space accesses. In the 82559ER, this bit is configurable and
		the default value of 0b.

48 Datasheet