Intel GD82559ER manual Interrupt Pin Register, Minimum Grant Register, Maximum Latency Register

GD82559ER — Networkin g Silicon

7.1.13Interrupt Pin Register

The Interrupt Pin register is read only and defines which of the four PCI interrupt request pins, INTA# through INTD#, a PCI device is connected to. The 82559ER is connected the INTA# pin.

7.1.14Minimum Grant Register

The Minimum Grant (Min_Gnt) register is an optional read only register for bus masters and is not applicable to non-master devices. It defines the amount of time the bus master wants to retain PCI bus ownership when it initiates a transaction. The default value of this register for the 82559ER is 08h. This can be converted to an actual time using the PCI specification (8* 1/PCIclk), to a value of 242ns.

7.1.15Maximum Latency Register

The Maximum Latency (Max_Lat) register is an optional read only register for bus masters and is not applicable to non-master devices. This register defines how often a device needs to access the PCI bus. The default value of this register for the 82559ER is 18h. This can be converted to an actual time using the PCI specification (18h* 1/PCIclk), to a value of 1μs.

7.1.16Capability ID Register

The Capability ID is a byte register. It signifies whether the current item in the linked list is the register defined for PCI Power Management. PCI Power Management has been assigned the value of 01H.

7.1.17Next Item Pointer

The Next Item Pointer is a byte register. It describes the location of the next item in the 82559ER’s capability list. Since power management is the last item in the list, this register is set to 0b.

7.1.18Power Management Capabilities Register

The Power Management Capabilities register is a word read only register. It provides information on the capabilities of the 82559ER related to power management. The 82559ER reports a value of FE21h if it is connected to an auxiliary power source and 7E21h otherwise. It indicates that the 82559ER supports wake-up in the D3 state if power is supplied, either Vcc or VAUX.

Table 8. Power Management Capability Register

Bits	Default	Read/Write	Description
31:27	00011b	Read Only	PME Support. This five bit field indicates the power states in which
	(no VAUX)		the 82559ER may assert PME#. The 82559ER supports wake-up in
	11111b		all power states if it is fed by an auxiliary power supply (VAUX) and
	(V )		D0, D1, D2, and D3hot if it is fed by PCI power.
	AUX
26	1b	Read Only	D2 Support. If this bit is set, the 82559ER supports the D2 power
			state.
25	1b	Read Only	D1 Support. If this bit is set, the 82559ER supports the D1 power
			state.

54 Datasheet