Intel GD82559ER manual PCI Timings, Flash Interface Timings, PCI Timing Parameters, Datasheet

Networking Silicon — GD82559ER

Table 24. Measure and Test Condition Parameters

Vstep (rising edge)	0.285VCC	0.325VCC	V	Min Delay
		0.475VCC	V	Max Delay
Vstep (falling edge)	0.615VCC	0.475VCC	V	Min Delay
		0.325VCC	V	Max Delay
Vmax	0.4VCC	0.4VCC	V
Input Signal Edge	1	1	V/ns
Rate

NOTE: Input test is done with 0.1VCC overdrive. Vmax specifies the maximum peak-to-peak waveform allowed for testing input timing.

10.4.2.2PCI Timings

Table 25. PCI Timing Parameters

	Symbol	Parameter	Min	Max	Units	Notes
T14	tval	PCI CLK to Signal Valid Delay	2	11	ns	1, 2, 4
T15	tval(ptp)	PCI CLK to Signal Valid Delay (point-	2	12	ns	1, 2, 4
		to-point)
T16	ton	Float to Active Delay	2		ns	1
T17	toff	Active to Float Delay		28	ns	1
T18	tsu	Input Setup Time to CLK	7		ns	4, 5
T19	tsu(ptp)	PCI Input Setup Time to CLK (point-to-	10		ns	4, 5
		point)
T20	th	Input Hold Time from CLK	0		ns	6
T21	trst	Reset Active Time After Power Stable	1		ms	6
T22	Trst-clk	PCI Reset Active Time After CLK	100		μs	6
		Stable
T23	Trst-off	Reset Active to Output Float Delay		40	ns	6, 7

NOTES:

1.Timing measurement conditions are illustrated in Figure 27.

2.PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section 4.2.3.2.

3.n a PCI environment, REQ# and GNT# are point-to-point signals and have different output valid delay times and input setup times than bussed signals. All other signals are bussed.

4.Timing measurement conditions are illustrated in Figure 28.

5.RST# is asserted and de-asserted asynchronously with respect to the CLK signal.

6.All PCI interface output drivers are floated when RST# is active.

10.4.2.3Flash Interface Timings

The 82559ER is designed to support up to 150 nanoseconds of Flash access time. The VPP signal in the Flash implementation should be connected permanently to 12 V. Thus, writing to the Flash is controlled only by the FLWE# pin.

Table 26 provides the timing parameters for the Flash interface signals. The timing parameters are illustrated in Figure 29.

Datasheet 79