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Intel manual Ethernet Data Register, GD82559ER - Networkin g Silicon, Datasheet

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GD82559ER — Networkin g Silicon

7.1.20Data Register

The data register is an 8-bit read only register that provides a mechanism for the 82559ER to report state dependent maximum power consumption and heat dissipation. The value reported in this register depends on the value written to the Data Select field in the PMCSR register. The power measurements defined in this register have a dynamic range of 0 to 2.55 W with 0.01 W resolution according to the Data Scale. The value in this register is hard coded in the silicon. The structure of the data register is presented below.

Table 10. Ethernet Data Register

Data Select	Data Scale		Data Reported


0	2	D0	Power Consumption = 60 (600 mW)

1	2	D1	Power Consumption = 42 (420 mW)

2	2	D2	Power Consumption = 42 (420 mW)

3	2	D3	Power Consumption = 42 (420 mW)

4	2	D0	Power Dissipated = 58 (580 mW)

5	2	D1	Power Dissipated = 40 (400 mW)

6	2	D2	Power Dissipated = 40 (400 mW)

7	2	D3	Power Dissipated = 40 (400 mW)

8	2	Common Function Power Dissipated = 00

9-15	0	Reserved (00H)

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Datasheet

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Intel manual Ethernet Data Register, GD82559ER - Networkin g Silicon, Datasheet

Contents

GD82559ER Fast Ethernet PCI Controller Product FeaturesDatasheet Networking SiliconRevision History DatasheetGD82559ER - Networking Silicon DateDatasheet ContentsINTRODUCTION SIGNAL DESCRIPTIONSDatasheet PCI CONFIGURATION REGISTERSCONTROL/STATUS REGISTERS GD82559ER - Networking SiliconDatasheet 10. ELECTRICAL AND TIMING SPECIFICATIONSNetworking Silicon - GD82559ER 8.1.10Datasheet GD82559ER - Networking Silicon1.2 Suggested Reading 1. Introduction1.1 GD82559ER Overview DatasheetGD82559ER - Networkin g Silicon Datasheet2.1 Parallel Subsystem Overview Figure 1. 82559ER Block Diagram2. GD82559ER Architectural Overview DatasheetGD82559ER - Networkin g Silicon 2.2 FIFO Subsystem OverviewDatasheet Datasheet 2.3 10/100 Mbps Serial CSMA/CD Unit Overview2.4 10/100 Mbps Physical Layer Unit Networking Silicon - GD82559ERDatasheet GD82559ER - Networkin g Silicon3.2 PCI Bus Interface Signals 3. Signal Descriptions3.1 Signal Type Definitions 3.2.1 Address and Data SignalsGD82559ER - Networkin g Silicon 3.2.2 Interface Control SignalsDatasheet Datasheet 3.3 Local Memory Interface Signals3.2.3 System and Power Management Signals Flash Address15/EEPROM Data Output. During Flash accessesFlash Address13/EEPROM Data Input. During Flash accesses 3.4 Testability Port SignalsDatasheet GD82559ER - Networkin g SiliconNetworking Silicon -GD82559ER 3.5 PHY SignalsDatasheet Reference Bias Resistor 100 Mbps. This pin controls the outDatasheet GD82559ER - Networkin g Silicon4.1.1 Initialization Effects on 82559ER Units 4. GD82559ER Media Access Control Functional Description4.1 82559ER Initialization Datasheet4.2.1 82559ER Bus Operations 4.2.1.1.1 Control/Status Register CSR Accesses4.2 PCI Interface 4.2.1.1 82559ER Bus Slave OperationFigure 2. CSR I/O Read Cycle SYSTEM82559ER Figure 3. CSR I/O Write CycleDatasheet 4.2.1.1.2 Flash Buffer AccessesFigure 4. Flash Buffer Read Cycle GD82559ER - Networkin g SiliconDatasheet 4.2.1.1.3 Retry Premature AccessesFigure 5. Flash Buffer Write Cycle Networking Silicon - GD82559ER82559ER SYSTEM 4.2.1.1.4 Error Handling4.2.1.2 82559ER Bus Master Operation Figure 6. PCI Retry CycleDatasheet Figure 7. Memory Read Burst CycleFigure 8. Memory Write Burst Cycle Networking Silicon - GD82559ERGD82559ER - Networkin g Silicon 4.2.1.2.1 Memory Write and InvalidateDatasheet Networking Silicon - GD82559ER 4.2.1.2.2 Read AlignDatasheet 4.2.1.2.3 Error Handling 4.2.2 Clockrun Signal4.2.3 Power Management Event Signal Datasheet4.2.4.2 D1 Power State 4.2.4 Power States4.2.4.1 D0 Power State 4.2.4.3 D2 Power StateDatasheet 4.2.4.4 D3 Power State4.2.4.5 Understanding Power Requirements Power State4.2.4.7.1 Isolate Signal 4.2.4.6 Auxiliary Power Signal4.2.4.7 Alternate Reset Signal DatasheetDatasheet 4.2.4.7.2 PCI Reset SignalFigure 9. Isolate Signal Behavior to PCI Power Good Signal GD82559ER - Networkin g SiliconFigure 10. 82559ER Initialization upon PCI RST# and ISOLATE# 4.2.5 Wake-up Events4.2.5.1 “Interestin g” Packet Events Datasheet4.2.5.2 Link Status Change Event 4.3 Parallel Flash Interface4.4 Serial EEPROM Interface DatasheetDatasheet Figure 11. 64 Word EEPROM Read Instruction WaveformFigure 12. 82559ER EEPROM Format Networking Silicon - GD82559ERDatasheet 4.5 10/100 Mbps CSMA/CD UnitTable 1. EEPROM Words Field Descriptions Word4.5.3 Address Filtering Modifications 4.5.1 Full Duplex4.5.2 Flow Control 4.5.4 Long Frame ReceptionGD82559ER - Networkin g Silicon 4.6 Media Independent Interface MII Management InterfaceDatasheet 5.2 Asynchronous Test Mode 5. GD82559ER Test Port Functionality5.1 Introduction 5.3 Test Function DescriptionTable 2. Nand - Tree Chains 5.5 TriState5.6 Nand - Tree DatasheetTable 2. Nand - Tree Chains DatasheetNetworking Silicon - GD82559ER FLA0Datasheet GD82559ER - Networkin g Silicon6.1.1 100BASE-TX Transmit Clock Generation 6. GD82559ER Physical Layer Functional Description6.1 100BASE-TX PHY Unit 6.1.2 100BASE-TX Transmit BlocksGD82559ER - Networkin g Silicon 6.1.2.2 100BASE-TX Scrambler and MLT-3 EncoderDatasheet Table 3. 4B/5B Encoder6.1.2.4 Transmit Driver Figure 13. NRZ to MLT-3 Encoding Diagram6.1.2.3 100BASE-TX Transmit Framing Figure 14. Conceptual Transmit Differential Waveform6.1.3 100BASE-TX Receive Blocks 6.1.3.2 Receive Clock and Data Recovery6.1.3.5 100BASE-TX Receive Error Detection and Reporting 6.1.3.1 Adaptive Equalizer6.1.4 100BASE-TX Collision Detection 6.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution6.2 10BASE-T Functionality 6.1.6 Auto 10/100 Mbps Speed Selection6.2.2.1 10BASE-T Manchester Encoder 6.2.2 10BASE-T Transmit Blocks6.2.3 10BASE-T Receive Blocks 6.2.2.2 10BASE-T Driver and Filter6.2.4 10BASE-T Collision Detection 6.2.3.3 10BASE-T Error Detection and Reporting6.3 Auto-Negotiation Functionality 6.2.5 10BASE-T Link IntegrityDatasheet 6.3.1 Description6.3.2 Parallel Detect and Auto-Negotiation GD82559ER - Networkin g SiliconDatasheet 6.4 LED DescriptionFigure 15. Auto-Negotiation and Parallel Detect Networking Silicon - GD82559ERGD82559ER - Networkin g Silicon Figure 16. Two and Three LED Schematic DiagramDatasheet LILEDFigure 17. PCI Configuration Registers 7. PCI Configuration Registers7.1 LAN Ethernet PCI Configuration Space 7.1.1 PCI Vendor ID and Device ID RegistersBus Master Enable Memory Space IO space 7.1.2 PCI Command RegisterSERR# Enable Parity Error Response Memory Write and Invalidate Enable Figure 18. PCI Command RegisterFigure 19. PCI Status Register 7.1.3 PCI Status Register1 0 Table 6. PCI Status Register Bits7.1.6 PCI Cache Line Size Register 7.1.4 PCI Revision ID Register7.1.5 PCI Class Code Register Figure 20. Cache Line Size Register7.1.9 PCI Base Address Registers 7.1.7 PCI Latency Timer7.1.8 PCI Header Type Figure 21. Base Address Register for Memory Mapping7.1.9.3 Flash Memory Mapped Base Address Register 7.1.9.1 CSR Memory Mapped Base Address Register7.1.9.2 CSR I/O Mapped Base Address Register 7.1.9.4 Expansion ROM Base Address Register7.1.12 Interrupt Line Register 7.1.10 PCI Subsystem Vendor ID and Subsystem ID Registers7.1.11 Capability Pointer Table 7. 82559ER ID Fields Programming7.1.13 Interrupt Pin Register 7.1.18 Power Management Capabilities RegisterTable 8. Power Management Capability Register 7.1.14 Minimum Grant RegisterTable 8. Power Management Capability Register 7.1.19 Power Management Control/Status Register PMCSRTable 9. Power Management Control and Status Register DatasheetDatasheet 7.1.20 Data RegisterTable 10. Ethernet Data Register GD82559ER - Networkin g Silicon8.1 LAN Ethernet Control/Status Registers SCB Status Word SCB Command Word SCB General Pointer PORT Interface8. Control/Status Registers Figure 23. 82559ER Control/Status RegisterDatasheet 8.1.1 System Control Block Status WordReceive DMA Byte Count Flow Control Register PMDR GD82559ER - Networking Silicon8.1.4 PORT 8.1.2 System Control Block Command Word8.1.3 System Control Block General Pointer 8.1.5 Flash Control RegisterTable 11. Power Management Driver Register 8.1.8 Receive Direct Memory Access Byte Count8.1.11 Power Management Driver Register 8.1.9 Early Receive InterruptTable 12. General Control Register 8.1.12 General Control Register8.1.13 General Status Register Table 13. General Status RegisterDatasheet 8.2 Statistical CountersTable 14. 82559ER Statistical Counters GD82559ER - Networking Siliconfollow the first are also lost however, because there is no lost DatasheetTable 14. 82559ER Statistical Counters frames. These frames are valid MAC control frames that haveDatasheet GD82559ER - Networking Silicon9.1.1 Register 0 Control Register Bit Definitions 9. PHY Unit Registers9.1 MDI Registers 0 DatasheetGD82559ER - Networking Silicon 9.1.2 Register 1 Status Register Bit DefinitionsDatasheet This bit restarts the Auto-Negotiation process and is selfDatasheet 9.1.3 Register 2 PHY Identifier Register Bit Definitions9.1.4 Register 3 PHY Identifier Register Bit Definitions Networking Silicon - GD82559ER9.1.7 Register 6 Auto-Negotiation Expansion Register Bit Definitions 9.2 MDI Registers 89.3 MDI Register 16 DatasheetNetworking Silicon - GD82559ER 9.3.2 Register 17 PHY Unit Special Control Bit DefinitionsDatasheet 9.3.3 Register 18 PHY Address Register Register 21 100BASE-TX Receive Error Frame Counter Bit9.3.7 Register 22 Receive Symbol Error Counter Bit Definitions 9.3.59.3.8 Register 23 100BASE-TX Receive Premature End of Frame ErrorRegister 24 10BASE-T Receive End of Frame Error Counter Bit Counter Bit DefinitionsDatasheet GD82559ER - Networking SiliconTable 15. General DC Specifications 10. Electrical and Timing Specifications10.2 DC Specifications Table 16. PCI Interface DC SpecificationsTable 19. 100BASE-TX Voltage/Current Characteristics Table 17. Flash/EEPROM Interface DC SpecificationsTable 18. LED Voltage/Current Characteristics Table 16. PCI Interface DC SpecificationsTable 19. 100BASE-TX Voltage/Current Characteristics Table 20. 10BASE-T Voltage/Current CharacteristicsFigure 24. RBIAS100 Resistance Versus Transmitter Current DatasheetFigure 25. RBIAS10 Resistance Versus Transmitter Current 10.3 AC SpecificationsTable 21. AC Specifications for PCI Signaling Datasheet10.4.1.1 PCI Clock Specifications 10.4 Timing Specifications10.4.1 Clocks Specifications 10.4.1.2 X1 SpecificationsFigure 27. Output Timing Measurement Conditions 10.4.2 Timing Parameters10.4.2.1 Measurement and Test Conditions Figure 28. Input Timing Measurement ConditionsTable 25. PCI Timing Parameters 10.4.2.2 PCI Timings10.4.2.3 Flash Interface Timings DatasheetGD82559ER - Networking Silicon Table 26. Flash Timing ParametersDatasheet Table 27. EEPROM Timing Parameters 10.4.2.4 EEPROM Interface TimingsFigure 29. Flash Timings for a Read Cycle DatasheetTable 28. 10BASE-T NLP Timing Parameters 10.4.2.5 PHY TimingsFigure 30. EEPROM Timings Figure 31. 10BASE-T NLP TimingsDatasheet Table 30. 100Base-TX Transmitter AC SpecificationFigure 32. Auto-Negotiation FLP Timings Networking Silicon - GD82559ERDatasheet GD82559ER - Networking Silicon12.1 Package Information Figure 24. Dimension Diagram for the GD82559ER 196-Pin BGA12. Package and Pinout Information DatasheetTable 15. GD82559ER Pin Assignments 12.2 Pinout Information12.2.1 GD82559ER Pin Assignments DatasheetTable 15. GD82559ER Pin Assignments DatasheetNetworking Silicon - GD82559ER Datasheet 12.2.2 GD82559ER Ball Grid Array DiagramFigure 25. GD82559ER Ball Grid Array Diagram GD82559ER - Networking Silicon