GD82559ER — Networkin g Silicon

 

 

Table 6. PCI Status Register Bits

 

 

 

Bits

Name

Description

 

 

 

 

 

 

 

 

This bit indicates whether a parity error has been detected. This bit is set to

 

 

1b when the following three conditions are met:

 

 

1. The bus agent asserted PERR# itself or observed PERR# asserted.

24

Parity Error Detected

2. The agent setting the bit acted as the bus master for the operation in

which the error occurred.

 

 

 

 

3. The Parity Error Response bit in the command register (bit 6) is set.

 

 

In the 82559ER, the initial value of the Parity Error Detected bit is 0b. This

 

 

bit is set until cleared by writing a 1b.

 

 

 

 

 

This bit indicates a device’s ability to accept fast back-to-back transactions

23

Fast Back-to-Back

when the transactions are not to the same agent. A value of 0b disables

fast back-to-back ability. A value of 1b enables fast back-to-back ability. In

 

 

 

 

the 82559ER, this bit is read only and is set to 1b.

 

 

 

 

 

This bit indicates whether the 82559ER implements a list of new

 

 

capabilities such as PCI Power Management. A value of 0b means that this

20

Capabilities List

function does not implement the Capabilities List. If this bit is set to 1b, the

Cap_Ptr register provides an offset into the 82559ER PCI Configuration

 

 

 

 

space pointing to the location of the first item in the Capabilities List. This

 

 

bit is set only if the power management bit in the EEPROM is set.

 

 

 

19:16

Reserved

These bits are reserved and should be set to 0000b.

 

 

 

7.1.4PCI Revision ID Register

The Revision ID is an 8-bit read only register with a default value of 08h for the 82559ER. The three least significant bits of the Revision ID can be overridden by the ID and Revision ID fields in the EEPROM (Section 4.4, “Serial EEPROM Interface” on page 28 ).

7.1.5PCI Class Code Register

The Class Code register is read only and is used to identify the generic function of the device and, in some cases, specific register level programming interface. The register is broken into three byte size fields. The upper byte is a base class code and specifies the 82559ER as a network controller, 2H. The middle byte is a subclass code and specifies the 82559ER as an Ethernet controller, 0H.

The lower byte identifies a specific register level programming interface and the 82559ER always returns a 0h in this field.

7.1.6PCI Cache Line Size Register

In order for the 82559ER to support the Memory Write and Invalidate (MWI) command, the 82559ER must also support the Cache Line Size (CLS) register in PCI Configuration space. The register supports only cache line sizes of 8 and 16 Dwords. Any value other than 8 or 16 that is written to the register is ignored and the 82559ER does not use the MWI command. If a value other than 8 or 16 is written into the CLS register, the 82559ER returns all zeroes when the CLS register is read. The figure below illustrates the format of this register.

7

6

5

4

3

2

1

0

0

0

0

RW

RW

0

0

0

Figure 20. Cache Line Size Register

50

Datasheet

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Intel GD82559ER manual PCI Revision ID Register, PCI Class Code Register, PCI Cache Line Size Register
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GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.
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