GD82559ER — Networkin g Silicon
controls the TRDY# signal and asserts it from the data access. The 82559ER allows the CPU to issue only one I/O write cycle to the Control/Status Registers, generating a disconnect by asserting the STOP# signal. This is true for both memory mapped and I/O mapped accesses.
The CPU accesses to the Flash buffer are very slow. For this reason the 82559ER issues a target- disconnect at the first data access. The 82559ER asserts the STOP# signal to indicate a target- disconnect. The figures below illustrate memory CPU read and write accesses to the 128 Kbyte Flash buffer. The longest burst cycle to the Flash buffer contains one data access only.
SYSTEM
CLK
FRAME#
AD
C/BE#
IRDY#
ADDR
MEM RD
BE#
DATA
82559ER
TRDY#
DEVSEL#
STOP#
Read Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82559ER controls the TRDY# signal and
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