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Intel GD82559ER manual Wake-up Events, 4.2.5.1 “Interestin g” Packet Events, Datasheet

Models: GD82559ER

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Networking Silicon — GD82559ER

•ISOLATE# trailing edge

The internal initialization signal resets the PCI Configuration Space, MAC configuration, and memory structure.

The behavior of the PCI RST# signal and the internal 82559ER initialization signal are shown in the figure below.

PCI RST#

Internal hardware reset

PCI RST#

Internal hardware reset

ISOLATE#

Internal hardware reset

D0 - D2 power state

D3 power state

640 ns

Internal reset

due to ISOLATE#

640 ns

Figure 10. 82559ER Initialization upon PCI RST# and ISOLATE#

4.2.5Wake-up Events

There are two types of wake-up events: “Interesting” Packets and Link Status Change. These two events are detailed below.

Note: The wake-up event is supported only if the PME Enable bit in the Power Management Control/ Status (PMCSR) register is set. (The PMCSR is described in Section 7.1.19, “Power Management Control/Status Register (PMCSR)” on page 55 .)

4.2.5.1“Interestin g” Packet Events

In the power-down state, the 82559ER is capable of recognizing “interesting” packets. The 82559ER supports pre-defined and programmable packets that can be defined as any of the following:

•ARP Packets (with Multiple IP addresses)

•Direct Packets (with or without type qualification)

•Neighbor Discovery Multicast Address Packet (‘ARP’ in IPv6 environment)

•NetBIOS over TCP/IP (NBT) Query Packet (under IPv4)

•Internetwork Package Exchange* (IPX) Diagnostic Packet

This allows the 82559ER to handle various packet types. In general, the 82559ER supports programmable filtering of any packet in the first 128 bytes.

Datasheet

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Intel GD82559ER Wake-up Events, 4.2.5.1 “Interestin g” Packet Events, 82559ER Initialization upon PCI RST# and ISOLATE#

Contents

Datasheet Product FeaturesGD82559ER Fast Ethernet PCI Controller Networking SiliconGD82559ER - Networking Silicon DatasheetRevision History DateINTRODUCTION ContentsDatasheet SIGNAL DESCRIPTIONSCONTROL/STATUS REGISTERS PCI CONFIGURATION REGISTERSDatasheet GD82559ER - Networking SiliconNetworking Silicon - GD82559ER 10. ELECTRICAL AND TIMING SPECIFICATIONSDatasheet 8.1.10GD82559ER - Networking Silicon Datasheet1.1 GD82559ER Overview 1. Introduction1.2 Suggested Reading DatasheetDatasheet GD82559ER - Networkin g Silicon2. GD82559ER Architectural Overview Figure 1. 82559ER Block Diagram2.1 Parallel Subsystem Overview Datasheet2.2 FIFO Subsystem Overview DatasheetGD82559ER - Networkin g Silicon 2.4 10/100 Mbps Physical Layer Unit 2.3 10/100 Mbps Serial CSMA/CD Unit OverviewDatasheet Networking Silicon - GD82559ERGD82559ER - Networkin g Silicon Datasheet3.1 Signal Type Definitions 3. Signal Descriptions3.2 PCI Bus Interface Signals 3.2.1 Address and Data Signals3.2.2 Interface Control Signals DatasheetGD82559ER - Networkin g Silicon 3.2.3 System and Power Management Signals 3.3 Local Memory Interface SignalsDatasheet Flash Address15/EEPROM Data Output. During Flash accessesDatasheet 3.4 Testability Port SignalsFlash Address13/EEPROM Data Input. During Flash accesses GD82559ER - Networkin g SiliconDatasheet 3.5 PHY SignalsNetworking Silicon -GD82559ER Reference Bias Resistor 100 Mbps. This pin controls the outGD82559ER - Networkin g Silicon Datasheet4.1 82559ER Initialization 4. GD82559ER Media Access Control Functional Description4.1.1 Initialization Effects on 82559ER Units Datasheet4.2 PCI Interface 4.2.1.1.1 Control/Status Register CSR Accesses4.2.1 82559ER Bus Operations 4.2.1.1 82559ER Bus Slave Operation82559ER SYSTEMFigure 2. CSR I/O Read Cycle Figure 3. CSR I/O Write CycleFigure 4. Flash Buffer Read Cycle 4.2.1.1.2 Flash Buffer AccessesDatasheet GD82559ER - Networkin g SiliconFigure 5. Flash Buffer Write Cycle 4.2.1.1.3 Retry Premature AccessesDatasheet Networking Silicon - GD82559ER4.2.1.2 82559ER Bus Master Operation 4.2.1.1.4 Error Handling82559ER SYSTEM Figure 6. PCI Retry CycleFigure 8. Memory Write Burst Cycle Figure 7. Memory Read Burst CycleDatasheet Networking Silicon - GD82559ER4.2.1.2.1 Memory Write and Invalidate DatasheetGD82559ER - Networkin g Silicon 4.2.1.2.2 Read Align DatasheetNetworking Silicon - GD82559ER 4.2.3 Power Management Event Signal 4.2.2 Clockrun Signal4.2.1.2.3 Error Handling Datasheet4.2.4.1 D0 Power State 4.2.4 Power States4.2.4.2 D1 Power State 4.2.4.3 D2 Power State4.2.4.5 Understanding Power Requirements 4.2.4.4 D3 Power StateDatasheet Power State4.2.4.7 Alternate Reset Signal 4.2.4.6 Auxiliary Power Signal4.2.4.7.1 Isolate Signal DatasheetFigure 9. Isolate Signal Behavior to PCI Power Good Signal 4.2.4.7.2 PCI Reset SignalDatasheet GD82559ER - Networkin g Silicon4.2.5.1 “Interestin g” Packet Events 4.2.5 Wake-up EventsFigure 10. 82559ER Initialization upon PCI RST# and ISOLATE# Datasheet4.4 Serial EEPROM Interface 4.3 Parallel Flash Interface4.2.5.2 Link Status Change Event DatasheetFigure 12. 82559ER EEPROM Format Figure 11. 64 Word EEPROM Read Instruction WaveformDatasheet Networking Silicon - GD82559ERTable 1. EEPROM Words Field Descriptions 4.5 10/100 Mbps CSMA/CD UnitDatasheet Word4.5.2 Flow Control 4.5.1 Full Duplex4.5.3 Address Filtering Modifications 4.5.4 Long Frame Reception4.6 Media Independent Interface MII Management Interface DatasheetGD82559ER - Networkin g Silicon 5.1 Introduction 5. GD82559ER Test Port Functionality5.2 Asynchronous Test Mode 5.3 Test Function Description5.6 Nand - Tree 5.5 TriStateTable 2. Nand - Tree Chains DatasheetNetworking Silicon - GD82559ER DatasheetTable 2. Nand - Tree Chains FLA0GD82559ER - Networkin g Silicon Datasheet6.1 100BASE-TX PHY Unit 6. GD82559ER Physical Layer Functional Description6.1.1 100BASE-TX Transmit Clock Generation 6.1.2 100BASE-TX Transmit BlocksDatasheet 6.1.2.2 100BASE-TX Scrambler and MLT-3 EncoderGD82559ER - Networkin g Silicon Table 3. 4B/5B Encoder6.1.2.3 100BASE-TX Transmit Framing Figure 13. NRZ to MLT-3 Encoding Diagram6.1.2.4 Transmit Driver Figure 14. Conceptual Transmit Differential Waveform6.1.3.5 100BASE-TX Receive Error Detection and Reporting 6.1.3.2 Receive Clock and Data Recovery6.1.3 100BASE-TX Receive Blocks 6.1.3.1 Adaptive Equalizer6.2 10BASE-T Functionality 6.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution6.1.4 100BASE-TX Collision Detection 6.1.6 Auto 10/100 Mbps Speed Selection6.2.3 10BASE-T Receive Blocks 6.2.2 10BASE-T Transmit Blocks6.2.2.1 10BASE-T Manchester Encoder 6.2.2.2 10BASE-T Driver and Filter6.3 Auto-Negotiation Functionality 6.2.3.3 10BASE-T Error Detection and Reporting6.2.4 10BASE-T Collision Detection 6.2.5 10BASE-T Link Integrity6.3.2 Parallel Detect and Auto-Negotiation 6.3.1 DescriptionDatasheet GD82559ER - Networkin g SiliconFigure 15. Auto-Negotiation and Parallel Detect 6.4 LED DescriptionDatasheet Networking Silicon - GD82559ERDatasheet Figure 16. Two and Three LED Schematic DiagramGD82559ER - Networkin g Silicon LILED7.1 LAN Ethernet PCI Configuration Space 7. PCI Configuration RegistersFigure 17. PCI Configuration Registers 7.1.1 PCI Vendor ID and Device ID RegistersSERR# Enable Parity Error Response Memory Write and Invalidate Enable 7.1.2 PCI Command RegisterBus Master Enable Memory Space IO space Figure 18. PCI Command Register1 0 7.1.3 PCI Status RegisterFigure 19. PCI Status Register Table 6. PCI Status Register Bits7.1.5 PCI Class Code Register 7.1.4 PCI Revision ID Register7.1.6 PCI Cache Line Size Register Figure 20. Cache Line Size Register7.1.8 PCI Header Type 7.1.7 PCI Latency Timer7.1.9 PCI Base Address Registers Figure 21. Base Address Register for Memory Mapping7.1.9.2 CSR I/O Mapped Base Address Register 7.1.9.1 CSR Memory Mapped Base Address Register7.1.9.3 Flash Memory Mapped Base Address Register 7.1.9.4 Expansion ROM Base Address Register7.1.11 Capability Pointer 7.1.10 PCI Subsystem Vendor ID and Subsystem ID Registers7.1.12 Interrupt Line Register Table 7. 82559ER ID Fields ProgrammingTable 8. Power Management Capability Register 7.1.18 Power Management Capabilities Register7.1.13 Interrupt Pin Register 7.1.14 Minimum Grant RegisterTable 9. Power Management Control and Status Register 7.1.19 Power Management Control/Status Register PMCSRTable 8. Power Management Capability Register DatasheetTable 10. Ethernet Data Register 7.1.20 Data RegisterDatasheet GD82559ER - Networkin g Silicon8. Control/Status Registers SCB Status Word SCB Command Word SCB General Pointer PORT Interface8.1 LAN Ethernet Control/Status Registers Figure 23. 82559ER Control/Status RegisterReceive DMA Byte Count Flow Control Register PMDR 8.1.1 System Control Block Status WordDatasheet GD82559ER - Networking Silicon8.1.3 System Control Block General Pointer 8.1.2 System Control Block Command Word8.1.4 PORT 8.1.5 Flash Control Register8.1.11 Power Management Driver Register 8.1.8 Receive Direct Memory Access Byte CountTable 11. Power Management Driver Register 8.1.9 Early Receive Interrupt8.1.13 General Status Register 8.1.12 General Control RegisterTable 12. General Control Register Table 13. General Status RegisterTable 14. 82559ER Statistical Counters 8.2 Statistical CountersDatasheet GD82559ER - Networking SiliconTable 14. 82559ER Statistical Counters Datasheetfollow the first are also lost however, because there is no lost frames. These frames are valid MAC control frames that haveGD82559ER - Networking Silicon Datasheet9.1 MDI Registers 0 9. PHY Unit Registers9.1.1 Register 0 Control Register Bit Definitions DatasheetDatasheet 9.1.2 Register 1 Status Register Bit DefinitionsGD82559ER - Networking Silicon This bit restarts the Auto-Negotiation process and is self9.1.4 Register 3 PHY Identifier Register Bit Definitions 9.1.3 Register 2 PHY Identifier Register Bit DefinitionsDatasheet Networking Silicon - GD82559ER9.3 MDI Register 16 9.2 MDI Registers 89.1.7 Register 6 Auto-Negotiation Expansion Register Bit Definitions Datasheet9.3.2 Register 17 PHY Unit Special Control Bit Definitions DatasheetNetworking Silicon - GD82559ER 9.3.7 Register 22 Receive Symbol Error Counter Bit Definitions Register 21 100BASE-TX Receive Error Frame Counter Bit9.3.3 Register 18 PHY Address Register 9.3.5Register 24 10BASE-T Receive End of Frame Error Counter Bit Register 23 100BASE-TX Receive Premature End of Frame Error9.3.8 Counter Bit DefinitionsGD82559ER - Networking Silicon Datasheet10.2 DC Specifications 10. Electrical and Timing SpecificationsTable 15. General DC Specifications Table 16. PCI Interface DC SpecificationsTable 18. LED Voltage/Current Characteristics Table 17. Flash/EEPROM Interface DC SpecificationsTable 19. 100BASE-TX Voltage/Current Characteristics Table 16. PCI Interface DC SpecificationsFigure 24. RBIAS100 Resistance Versus Transmitter Current Table 20. 10BASE-T Voltage/Current CharacteristicsTable 19. 100BASE-TX Voltage/Current Characteristics DatasheetTable 21. AC Specifications for PCI Signaling 10.3 AC SpecificationsFigure 25. RBIAS10 Resistance Versus Transmitter Current Datasheet10.4.1 Clocks Specifications 10.4 Timing Specifications10.4.1.1 PCI Clock Specifications 10.4.1.2 X1 Specifications10.4.2.1 Measurement and Test Conditions 10.4.2 Timing ParametersFigure 27. Output Timing Measurement Conditions Figure 28. Input Timing Measurement Conditions10.4.2.3 Flash Interface Timings 10.4.2.2 PCI TimingsTable 25. PCI Timing Parameters DatasheetTable 26. Flash Timing Parameters DatasheetGD82559ER - Networking Silicon Figure 29. Flash Timings for a Read Cycle 10.4.2.4 EEPROM Interface TimingsTable 27. EEPROM Timing Parameters DatasheetFigure 30. EEPROM Timings 10.4.2.5 PHY TimingsTable 28. 10BASE-T NLP Timing Parameters Figure 31. 10BASE-T NLP TimingsFigure 32. Auto-Negotiation FLP Timings Table 30. 100Base-TX Transmitter AC SpecificationDatasheet Networking Silicon - GD82559ERGD82559ER - Networking Silicon Datasheet12. Package and Pinout Information Figure 24. Dimension Diagram for the GD82559ER 196-Pin BGA12.1 Package Information Datasheet12.2.1 GD82559ER Pin Assignments 12.2 Pinout InformationTable 15. GD82559ER Pin Assignments DatasheetDatasheet Networking Silicon - GD82559ERTable 15. GD82559ER Pin Assignments Figure 25. GD82559ER Ball Grid Array Diagram 12.2.2 GD82559ER Ball Grid Array DiagramDatasheet GD82559ER - Networking Silicon