Intel GD82559ER manual Signal Descriptions, Signal Type Definitions, PCI Bus Interface Signals

Networking Silicon —GD82559ER

3.Signal Descriptions

3.1Signal Type Definitions

Type	Name	Description
IN	Input	The input pin is a standard input only signal.
OUT	Output	The output pin is a Totem Pole Output pin and is a standard
		active driver.
T/S	Tri-State	The tri-state pin is a bidirectional, input/output pin.
		The sustained tri-state pin is an active low tri-state signal owned
		and driven by one agent at a time. The agent asserting the S/T/
S/T/S	Sustained Tri-State	S pin low must drive it high at least one clock cycle before
		floating the pin. A new agent can only assert an S/T/S signal low
		one clock cycle after it has been tri-stated by the previous
		owner.
O/D	Open Drain	The open drain pin allows multiple devices to share this signal
		as a wired-OR.
A/I	Analog Input	The analog input pin is used for analog input signals.
A/O	Analog Output	The analog output pin is used for analog output signals.
B	Bias	The bias pin is an input bias.

3.2PCI Bus Interface Signals

3.2.1Address and Data Signals

Symbol	Type	Name and Function
		Address and Data. The address and data lines are multiplexed on
		the same PCI pins. A bus transaction consists of an address phase
		followed by one or more data phases. During the address phase, the
		address and data lines contain the 32-bit physical address. For I/O,
AD[31:0]	T/S	this is a byte address; for configuration and memory, it is a Dword
		address. The 82559ER uses little-endian byte ordering (in other
		words, AD[31:24] contain the most significant byte and AD[7:0]
		contain the least significant byte). During the data phases, the address
		and data lines contain data.
		Command and Byte Enable. The bus command and byte enable
		signals are multiplexed on the same PCI pins. During the address
C/BE[3:0]#	T/S	phase, the C/BE# lines define the bus command. During the data
		phase, the C/BE# lines are used as Byte Enables. The Byte Enables
		are valid for the entire data phase and determine which byte lanes
		carry meaningful data.
		Parity. Parity is even across AD[31:0] and C/BE[3:0]# lines. It is stable
		and valid one clock after the address phase. For data phases, PAR is
		stable and valid one clock after either IRDY# is asserted on a write
PAR	T/S	transaction or TRDY# is asserted on a read transaction.Once PAR is
		valid, it remains valid until one clock after the completion of the current
		data phase. The master drives PAR for address and write data
		phases; and the target, for read data phases.

Datasheet 7