Networking Silicon —GD82559ER

3.Signal Descriptions

3.1Signal Type Definitions

Type

Name

Description

 

 

 

 

 

 

IN

Input

The input pin is a standard input only signal.

 

 

 

OUT

Output

The output pin is a Totem Pole Output pin and is a standard

active driver.

 

 

 

 

 

T/S

Tri-State

The tri-state pin is a bidirectional, input/output pin.

 

 

 

 

 

The sustained tri-state pin is an active low tri-state signal owned

 

 

and driven by one agent at a time. The agent asserting the S/T/

S/T/S

Sustained Tri-State

S pin low must drive it high at least one clock cycle before

floating the pin. A new agent can only assert an S/T/S signal low

 

 

 

 

one clock cycle after it has been tri-stated by the previous

 

 

owner.

 

 

 

O/D

Open Drain

The open drain pin allows multiple devices to share this signal

as a wired-OR.

 

 

 

 

 

A/I

Analog Input

The analog input pin is used for analog input signals.

 

 

 

A/O

Analog Output

The analog output pin is used for analog output signals.

 

 

 

B

Bias

The bias pin is an input bias.

 

 

 

3.2PCI Bus Interface Signals

3.2.1Address and Data Signals

Symbol

Type

Name and Function

 

 

 

 

 

 

 

 

Address and Data. The address and data lines are multiplexed on

 

 

the same PCI pins. A bus transaction consists of an address phase

 

 

followed by one or more data phases. During the address phase, the

 

 

address and data lines contain the 32-bit physical address. For I/O,

AD[31:0]

T/S

this is a byte address; for configuration and memory, it is a Dword

 

 

address. The 82559ER uses little-endian byte ordering (in other

 

 

words, AD[31:24] contain the most significant byte and AD[7:0]

 

 

contain the least significant byte). During the data phases, the address

 

 

and data lines contain data.

 

 

 

 

 

Command and Byte Enable. The bus command and byte enable

 

 

signals are multiplexed on the same PCI pins. During the address

C/BE[3:0]#

T/S

phase, the C/BE# lines define the bus command. During the data

phase, the C/BE# lines are used as Byte Enables. The Byte Enables

 

 

 

 

are valid for the entire data phase and determine which byte lanes

 

 

carry meaningful data.

 

 

 

 

 

Parity. Parity is even across AD[31:0] and C/BE[3:0]# lines. It is stable

 

 

and valid one clock after the address phase. For data phases, PAR is

 

 

stable and valid one clock after either IRDY# is asserted on a write

PAR

T/S

transaction or TRDY# is asserted on a read transaction.Once PAR is

 

 

valid, it remains valid until one clock after the completion of the current

 

 

data phase. The master drives PAR for address and write data

 

 

phases; and the target, for read data phases.

 

 

 

Datasheet

7

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Intel GD82559ER manual Signal Descriptions, Signal Type Definitions, PCI Bus Interface Signals, Address and Data Signals

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.