Intel GD82559ER manual Register 23 100BASE-TX Receive Premature End of Frame Error

Networking Silicon — GD82559ER

9.3.8	Register 23: 100BASE-TX Receive Premature End of Frame Error
	Counter Bit Definitions
		Bit(s)	Name	Description	Default	R/W
		15:0	Premature End of	This field contains a 16-bit counter that increments for	--	RO
			Frame	each premature end of frame event. The counter		SC
				freezes when full and self-clears on read.

9.3.9	Register 24: 10BASE-T Receive End of Frame Error Counter Bit
	Definitions
		Bit(s)	Name	Description	Default	R/W
		15:0	End of Frame	This is a 16-bit counter that increments for each end	--	RO
			Counter	of frame error event. The counter freezes when full		SC
				and self-clears on read.

9.3.10	Register 25: 10BASE-T Transmit Jabber Detect Counter Bit
	Definitions
		Bit(s)	Name	Description	Default	R/W
		15:0	Jabber Detect	This is a 16-bit counter that increments for each	--	RO
			Counter	jabber detection event. The counter freezes when full		SC
				and self-clears on read.

9.3.11	Register 26: Equalizer Control and Status Bit Definitions
		Bit(s)	Name	Description	Default	R/W
		15:0	RFU	Reserved for Future Use	--	RW

9.3.12Register 27: PHY Unit Special Control Bit Definitions

Bit(s)	Name		Description		Default	R/W
15:3	Reserved	These bits are reserved and should be set to 0b.			0	RW
2:0	LED Switch	Value	ACTLED	LILED	000	RW
	Control	000	Activity	Link
		001	Speed	Collision
		010	Speed	Link
		011	Activity	Collision
		100	Off	Off
		101	Off	On
		110	On	Off
		111	On	On

Datasheet 71