Intel GD82559ER specs

GD82559ER — Networkin g Silicon

4.6Media Independent Interface (MII) Management Interface

The MII management interface allows the CPU to control the PHY unit via a control register in the 82559ER. This allows the software driver to place the PHY in specific modes such as full duplex, loopback, power down, etc., without the need for specific hardware pins to select the desired mode. This structure allows the 82559ER to query the PHY unit for status of the link. This register is the MDI Control Register and resides at offset 10h in the 82559ER CSR. (The MDI registers are described in detail in Section 9., “PHY Unit Registers” on page 65 .) The CPU writes commands to this register and the 82559ER reads or writes the control/status parameters to the PHY unit through the MDI register. Although the 82559ER follows the MII format, the MI bus is not accessible on external pins.

Datasheet

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Intel GD82559ER manual Media Independent Interface MII Management Interface

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.

Contents

Product Features GD82559ER Fast Ethernet PCI Controller Revision Description Mar First release Contents PCI Configuration Registers Electrical and Timing Specifications GD82559ER Networking Silicon Datasheet Suggested Reading IntroductionGD82559ER Overview GD82559ER Networkin g Silicon Datasheet GD82559ER Architectural Overview Parallel Subsystem Overview Fifo Subsystem Overview GD82559ER Networkin g Silicon 10/100 Mbps Serial CSMA/CD Unit Overview 10/100 Mbps Physical Layer Unit GD82559ER Networkin g Silicon Datasheet PCI Bus Interface Signals Signal DescriptionsSignal Type Definitions Address and Data Signals Interface Control Signals Local Memory Interface Signals System and Power Management Signals Testability Port Signals PHY Signals GD82559ER Networkin g Silicon Datasheet Initialization Effects on 82559ER Units GD82559ER Media Access Control Functional Description82559ER Initialization D3 to D0 Software Selective 1 82559ER Bus Operations Control/Status Register CSR AccessesPCI Interface 1.1 82559ER Bus Slave Operation CSR I/O Read Cycle Flash Buffer Accesses Flash Buffer Read Cycle Retry Premature Accesses Flash Buffer Write Cycle Error Handling 1.2 82559ER Bus Master Operation Memory Read Burst Cycle Memory Write and Invalidate Read Align Clockrun Signal Power Management Event Signal 4.2 D1 Power State Power States4.1 D0 Power State 4.3 D2 Power State Power State Conditions 100 Mbs 10 Mbs 4.4 D3 Power StateUnderstanding Power Requirements PCI CLK Isolate Signal Auxiliary Power SignalAlternate Reset Signal Power State Link 82559ER Functionality PCI Reset Signal Isolate Signal Behavior to PCI Power Good Signal Wake-up Events Interestin g Packet Events Link Status Change Event Parallel Flash InterfaceSerial Eeprom Interface Word IA Byte Subsystem ID Bits Name Description 10/100 Mbps CSMA/CD UnitEeprom Words Field Descriptions ALL Address Filtering Modifications Full DuplexFlow Control Long Frame Reception Media Independent Interface MII Management Interface Introduction Asynchronous Test ModeGD82559ER Test Port Functionality Test Function Description Nand Tree Chains TriStateNand Tree Chain Order FLD7 STOP# FLD2 GNT# FLD3 PERR# FLD4 PAR FLD5FLD6 AD9 GD82559ER Networkin g Silicon Datasheet 1 100BASE-TX Transmit Clock Generation GD82559ER Physical Layer Functional Description100BASE-TX PHY Unit 2 100BASE-TX Transmit Blocks 2.2 100BASE-TX Scrambler and MLT-3 Encoder Invalid Magnetics Modules 2.3 100BASE-TX Transmit FramingTransmit Driver Vendor Model/Type 3 100BASE-TX Receive Blocks 4 100BASE-TX Collision Detection 5 100BASE-TX Link Integrity and Auto-Negotiation Solution10BASE-T Functionality Auto 10/100 Mbps Speed Selection 2.1 10BASE-T Manchester Encoder 2 10BASE-T Transmit Blocks3 10BASE-T Receive Blocks 2.2 10BASE-T Driver and Filter 5 10BASE-T Link Integrity Auto-Negotiation Functionality4 10BASE-T Collision Detection 6 10BASE-T Jabber Control Function Description Parallel Detect and Auto-Negotiation LED Description Auto-Negotiation and Parallel Detect Two and Three LED Schematic Diagram Liled T L E D PCI Vendor ID and Device ID Registers PCI Configuration RegistersLAN Ethernet PCI Configuration Space PCI Command Register PCI Command Register PCI Command Register Bits PCI Status Register PCI Status Register PCI Status Register Bits PCI Cache Line Size Register PCI Revision ID RegisterPCI Class Code Register PCI Base Address Registers PCI Latency TimerPCI Header Type Flash Memory Mapped Base Address Register CSR Memory Mapped Base Address RegisterCSR I/O Mapped Base Address Register Expansion ROM Base Address Register Interrupt Line Register PCI Subsystem Vendor ID and Subsystem ID RegistersCapability Pointer ER ID Fields Programming Minimum Grant Register Power Management Capabilities RegisterInterrupt Pin Register Maximum Latency Register Power Management Control/Status Register Pmcsr Power Management Control and Status Register Data Select Data Scale Data Reported Data RegisterEthernet Data Register D31 Control/Status RegistersLAN Ethernet Control/Status Registers D16 D15 Lower Word Offset System Control Block Status Word Port System Control Block Command WordSystem Control Block General Pointer Flash Control Register Power Management Driver Register Receive Direct Memory Access Byte CountPower Management Driver Register Early Receive Interrupt General Control Register General Control RegisterGeneral Status Register General Status Register Counter Description Statistical CountersER Statistical Counters Frame indicator, they are not counted GD82559ER Networking Silicon Datasheet MDI Registers 0 Bits Name Description DefaultPHY Unit Registers Register 0 Control Register Bit Definitions Register 1 Status Register Bit Definitions Register 3 PHY Identifier Register Bit Definitions Bits Name Description Default 150Register 2 PHY Identifier Register Bit Definitions Value 0154H 100BASE-TX MDI Registers 8MDI Register 16 10BASE-T Register 17 PHY Unit Special Control Bit Definitions Bits Register 22 Receive Symbol Error Counter Bit DefinitionsRegister 18 PHY Address Register Register 26 Equalizer Control and Status Bit Definitions Register 23 100BASE-TX Receive Premature End of Frame ErrorCounter Bit Definitions Register 27 PHY Unit Special Control Bit Definitions GD82559ER Networking Silicon Datasheet General DC Specifications Electrical and Timing SpecificationsDC Specifications PCI Interface DC Specifications BASE-TX Voltage/Current Characteristics Flash/EEPROM Interface DC SpecificationsLED Voltage/Current Characteristics VCC/2 BASE-T Voltage/Current CharacteristicsSymbol Parameter AC Specifications AC Specifications for PCI Signaling PCI Clock Specifications Timing SpecificationsClocks Specifications 10.4.1.2 X1 Specifications Measurement and Test Conditions Symbol PCI Level UnitsTiming Parameters Flash Interface Timings Symbol Parameter Min Max UnitsPCI Timings PCI Timing Parameters Flash Timing Parameters Eeprom Interface Timings Eeprom Timing Parameters PHY Timings Symbol Parameter Condition Min Typ Max UnitsSymbol Parameter Min Typ Max BASE-T NLP Timing Parameters Symbol Parameter Condition Min Typ Max Units T64 TDP/TDN Differential HLS Data 1400 Output Peak Jitter GD82559ER Networking Silicon Datasheet Package and Pinout Information Package Information GD82559ER Pin Assignments Pinout Information12.2.1 GD82559ER Pin Assignments Pin Name FLA1 STOP# INTA# DEVSEL# VCC VSSPERR# GNT# VCC FLA0 12.2.2 GD82559ER Ball Grid Array Diagram GD82559ER Ball Grid Array Diagram