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Intel GD82559ER Timing Parameters, Measurement and Test Conditions, C L K, Tri-State O U T P U T

Models: GD82559ER

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GD82559ER — Networking Silicon

10.4.2Timing Parameters

10.4.2.1Measurement and Test Conditions

Figure 27, Figure 28, and Table 24 define the conditions under which timing measurements are done. The component test guarantees that all timings are met with minimum clock slew rate (slowest edge) and voltage swing. The design must guarantee that minimum timings are also met with maximum clock slew rate (fastest edge) and voltage swing. In addition, the design must guarantee proper input operation for input voltage swings and slew rates that exceed the specified test conditions.

C L K

O U T P U T D E L A Y

Tri-State

O U T P U T

V_th

V_test

V_tl

T_val

V_step

V_test V_test

T_on

T_off

Figure 27. Output Timing Measurement Conditions

C L K

V_th

I N P U T

V_test

V_tl

V_test

T_su

T_h

inputs

valid

V_th

V_tl

V_test V_max

Figure 28. Input Timing Measurement Conditions

Table 24. Measure and Test Condition Parameters

Symbol	PCI Level	Units	Notes

Vth	0.6VCC	V
Vtl	0.2VCC	V
Vtest	0.4VCC	V

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Datasheet

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Intel GD82559ER Timing Parameters, Measurement and Test Conditions, Output Timing Measurement Conditions, C L K, I N P U T

Contents

Product Features DatasheetGD82559ER Fast Ethernet PCI Controller Networking SiliconDatasheet GD82559ER - Networking SiliconRevision History DateContents INTRODUCTIONDatasheet SIGNAL DESCRIPTIONSPCI CONFIGURATION REGISTERS CONTROL/STATUS REGISTERSDatasheet GD82559ER - Networking Silicon10. ELECTRICAL AND TIMING SPECIFICATIONS Networking Silicon - GD82559ERDatasheet 8.1.10Datasheet GD82559ER - Networking Silicon1. Introduction 1.1 GD82559ER Overview1.2 Suggested Reading DatasheetGD82559ER - Networkin g Silicon DatasheetFigure 1. 82559ER Block Diagram 2. GD82559ER Architectural Overview2.1 Parallel Subsystem Overview Datasheet2.2 FIFO Subsystem Overview DatasheetGD82559ER - Networkin g Silicon 2.3 10/100 Mbps Serial CSMA/CD Unit Overview 2.4 10/100 Mbps Physical Layer UnitDatasheet Networking Silicon - GD82559ERDatasheet GD82559ER - Networkin g Silicon3. Signal Descriptions 3.1 Signal Type Definitions3.2 PCI Bus Interface Signals 3.2.1 Address and Data Signals3.2.2 Interface Control Signals DatasheetGD82559ER - Networkin g Silicon 3.3 Local Memory Interface Signals 3.2.3 System and Power Management SignalsDatasheet Flash Address15/EEPROM Data Output. During Flash accesses3.4 Testability Port Signals DatasheetFlash Address13/EEPROM Data Input. During Flash accesses GD82559ER - Networkin g Silicon3.5 PHY Signals DatasheetNetworking Silicon -GD82559ER Reference Bias Resistor 100 Mbps. This pin controls the outDatasheet GD82559ER - Networkin g Silicon4. GD82559ER Media Access Control Functional Description 4.1 82559ER Initialization4.1.1 Initialization Effects on 82559ER Units Datasheet4.2.1.1.1 Control/Status Register CSR Accesses 4.2 PCI Interface4.2.1 82559ER Bus Operations 4.2.1.1 82559ER Bus Slave OperationSYSTEM 82559ERFigure 2. CSR I/O Read Cycle Figure 3. CSR I/O Write Cycle4.2.1.1.2 Flash Buffer Accesses Figure 4. Flash Buffer Read CycleDatasheet GD82559ER - Networkin g Silicon4.2.1.1.3 Retry Premature Accesses Figure 5. Flash Buffer Write CycleDatasheet Networking Silicon - GD82559ER4.2.1.1.4 Error Handling 4.2.1.2 82559ER Bus Master Operation82559ER SYSTEM Figure 6. PCI Retry CycleFigure 7. Memory Read Burst Cycle Figure 8. Memory Write Burst CycleDatasheet Networking Silicon - GD82559ER4.2.1.2.1 Memory Write and Invalidate DatasheetGD82559ER - Networkin g Silicon 4.2.1.2.2 Read Align DatasheetNetworking Silicon - GD82559ER 4.2.2 Clockrun Signal 4.2.3 Power Management Event Signal4.2.1.2.3 Error Handling Datasheet4.2.4 Power States 4.2.4.1 D0 Power State4.2.4.2 D1 Power State 4.2.4.3 D2 Power State4.2.4.4 D3 Power State 4.2.4.5 Understanding Power RequirementsDatasheet Power State4.2.4.6 Auxiliary Power Signal 4.2.4.7 Alternate Reset Signal4.2.4.7.1 Isolate Signal Datasheet4.2.4.7.2 PCI Reset Signal Figure 9. Isolate Signal Behavior to PCI Power Good SignalDatasheet GD82559ER - Networkin g Silicon4.2.5 Wake-up Events 4.2.5.1 “Interestin g” Packet EventsFigure 10. 82559ER Initialization upon PCI RST# and ISOLATE# Datasheet4.3 Parallel Flash Interface 4.4 Serial EEPROM Interface4.2.5.2 Link Status Change Event DatasheetFigure 11. 64 Word EEPROM Read Instruction Waveform Figure 12. 82559ER EEPROM FormatDatasheet Networking Silicon - GD82559ER4.5 10/100 Mbps CSMA/CD Unit Table 1. EEPROM Words Field DescriptionsDatasheet Word4.5.1 Full Duplex 4.5.2 Flow Control4.5.3 Address Filtering Modifications 4.5.4 Long Frame Reception4.6 Media Independent Interface MII Management Interface DatasheetGD82559ER - Networkin g Silicon 5. GD82559ER Test Port Functionality 5.1 Introduction5.2 Asynchronous Test Mode 5.3 Test Function Description5.5 TriState 5.6 Nand - TreeTable 2. Nand - Tree Chains DatasheetDatasheet Networking Silicon - GD82559ERTable 2. Nand - Tree Chains FLA0Datasheet GD82559ER - Networkin g Silicon6. GD82559ER Physical Layer Functional Description 6.1 100BASE-TX PHY Unit6.1.1 100BASE-TX Transmit Clock Generation 6.1.2 100BASE-TX Transmit Blocks6.1.2.2 100BASE-TX Scrambler and MLT-3 Encoder DatasheetGD82559ER - Networkin g Silicon Table 3. 4B/5B EncoderFigure 13. NRZ to MLT-3 Encoding Diagram 6.1.2.3 100BASE-TX Transmit Framing6.1.2.4 Transmit Driver Figure 14. Conceptual Transmit Differential Waveform6.1.3.2 Receive Clock and Data Recovery 6.1.3.5 100BASE-TX Receive Error Detection and Reporting6.1.3 100BASE-TX Receive Blocks 6.1.3.1 Adaptive Equalizer6.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution 6.2 10BASE-T Functionality6.1.4 100BASE-TX Collision Detection 6.1.6 Auto 10/100 Mbps Speed Selection6.2.2 10BASE-T Transmit Blocks 6.2.3 10BASE-T Receive Blocks6.2.2.1 10BASE-T Manchester Encoder 6.2.2.2 10BASE-T Driver and Filter6.2.3.3 10BASE-T Error Detection and Reporting 6.3 Auto-Negotiation Functionality6.2.4 10BASE-T Collision Detection 6.2.5 10BASE-T Link Integrity6.3.1 Description 6.3.2 Parallel Detect and Auto-NegotiationDatasheet GD82559ER - Networkin g Silicon6.4 LED Description Figure 15. Auto-Negotiation and Parallel DetectDatasheet Networking Silicon - GD82559ERFigure 16. Two and Three LED Schematic Diagram DatasheetGD82559ER - Networkin g Silicon LILED7. PCI Configuration Registers 7.1 LAN Ethernet PCI Configuration SpaceFigure 17. PCI Configuration Registers 7.1.1 PCI Vendor ID and Device ID Registers7.1.2 PCI Command Register SERR# Enable Parity Error Response Memory Write and Invalidate EnableBus Master Enable Memory Space IO space Figure 18. PCI Command Register7.1.3 PCI Status Register 1 0Figure 19. PCI Status Register Table 6. PCI Status Register Bits7.1.4 PCI Revision ID Register 7.1.5 PCI Class Code Register7.1.6 PCI Cache Line Size Register Figure 20. Cache Line Size Register7.1.7 PCI Latency Timer 7.1.8 PCI Header Type7.1.9 PCI Base Address Registers Figure 21. Base Address Register for Memory Mapping7.1.9.1 CSR Memory Mapped Base Address Register 7.1.9.2 CSR I/O Mapped Base Address Register7.1.9.3 Flash Memory Mapped Base Address Register 7.1.9.4 Expansion ROM Base Address Register7.1.10 PCI Subsystem Vendor ID and Subsystem ID Registers 7.1.11 Capability Pointer7.1.12 Interrupt Line Register Table 7. 82559ER ID Fields Programming7.1.18 Power Management Capabilities Register Table 8. Power Management Capability Register7.1.13 Interrupt Pin Register 7.1.14 Minimum Grant Register7.1.19 Power Management Control/Status Register PMCSR Table 9. Power Management Control and Status RegisterTable 8. Power Management Capability Register Datasheet7.1.20 Data Register Table 10. Ethernet Data RegisterDatasheet GD82559ER - Networkin g SiliconSCB Status Word SCB Command Word SCB General Pointer PORT Interface 8. Control/Status Registers8.1 LAN Ethernet Control/Status Registers Figure 23. 82559ER Control/Status Register8.1.1 System Control Block Status Word Receive DMA Byte Count Flow Control Register PMDRDatasheet GD82559ER - Networking Silicon8.1.2 System Control Block Command Word 8.1.3 System Control Block General Pointer8.1.4 PORT 8.1.5 Flash Control Register8.1.8 Receive Direct Memory Access Byte Count 8.1.11 Power Management Driver RegisterTable 11. Power Management Driver Register 8.1.9 Early Receive Interrupt8.1.12 General Control Register 8.1.13 General Status RegisterTable 12. General Control Register Table 13. General Status Register8.2 Statistical Counters Table 14. 82559ER Statistical CountersDatasheet GD82559ER - Networking SiliconDatasheet Table 14. 82559ER Statistical Countersfollow the first are also lost however, because there is no lost frames. These frames are valid MAC control frames that haveDatasheet GD82559ER - Networking Silicon9. PHY Unit Registers 9.1 MDI Registers 09.1.1 Register 0 Control Register Bit Definitions Datasheet9.1.2 Register 1 Status Register Bit Definitions DatasheetGD82559ER - Networking Silicon This bit restarts the Auto-Negotiation process and is self9.1.3 Register 2 PHY Identifier Register Bit Definitions 9.1.4 Register 3 PHY Identifier Register Bit DefinitionsDatasheet Networking Silicon - GD82559ER9.2 MDI Registers 8 9.3 MDI Register 169.1.7 Register 6 Auto-Negotiation Expansion Register Bit Definitions Datasheet9.3.2 Register 17 PHY Unit Special Control Bit Definitions DatasheetNetworking Silicon - GD82559ER Register 21 100BASE-TX Receive Error Frame Counter Bit 9.3.7 Register 22 Receive Symbol Error Counter Bit Definitions9.3.3 Register 18 PHY Address Register 9.3.5Register 23 100BASE-TX Receive Premature End of Frame Error Register 24 10BASE-T Receive End of Frame Error Counter Bit9.3.8 Counter Bit DefinitionsDatasheet GD82559ER - Networking Silicon10. Electrical and Timing Specifications 10.2 DC SpecificationsTable 15. General DC Specifications Table 16. PCI Interface DC SpecificationsTable 17. Flash/EEPROM Interface DC Specifications Table 18. LED Voltage/Current CharacteristicsTable 19. 100BASE-TX Voltage/Current Characteristics Table 16. PCI Interface DC SpecificationsTable 20. 10BASE-T Voltage/Current Characteristics Figure 24. RBIAS100 Resistance Versus Transmitter CurrentTable 19. 100BASE-TX Voltage/Current Characteristics Datasheet10.3 AC Specifications Table 21. AC Specifications for PCI SignalingFigure 25. RBIAS10 Resistance Versus Transmitter Current Datasheet10.4 Timing Specifications 10.4.1 Clocks Specifications10.4.1.1 PCI Clock Specifications 10.4.1.2 X1 Specifications10.4.2 Timing Parameters 10.4.2.1 Measurement and Test ConditionsFigure 27. Output Timing Measurement Conditions Figure 28. Input Timing Measurement Conditions10.4.2.2 PCI Timings 10.4.2.3 Flash Interface TimingsTable 25. PCI Timing Parameters DatasheetTable 26. Flash Timing Parameters DatasheetGD82559ER - Networking Silicon 10.4.2.4 EEPROM Interface Timings Figure 29. Flash Timings for a Read CycleTable 27. EEPROM Timing Parameters Datasheet10.4.2.5 PHY Timings Figure 30. EEPROM TimingsTable 28. 10BASE-T NLP Timing Parameters Figure 31. 10BASE-T NLP TimingsTable 30. 100Base-TX Transmitter AC Specification Figure 32. Auto-Negotiation FLP TimingsDatasheet Networking Silicon - GD82559ERDatasheet GD82559ER - Networking SiliconFigure 24. Dimension Diagram for the GD82559ER 196-Pin BGA 12. Package and Pinout Information12.1 Package Information Datasheet12.2 Pinout Information 12.2.1 GD82559ER Pin AssignmentsTable 15. GD82559ER Pin Assignments DatasheetDatasheet Networking Silicon - GD82559ERTable 15. GD82559ER Pin Assignments 12.2.2 GD82559ER Ball Grid Array Diagram Figure 25. GD82559ER Ball Grid Array DiagramDatasheet GD82559ER - Networking Silicon