GD82559ER — Networkin g Silicon

6.2.210BASE-T Transmit Blocks

6.2.2.110BASE-T Manchester Encoder

After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock performs the Manchester encoding. The Manchester code always has a mid-bit transition. If the value is 1b then the transition is from low to high. If the value is 0b then the transition is from high to low. The boundary transition occurs only when the data changes from bit to bit. For example, if the value is 10b, then the change is from high to low; if 01b, then the change is from low to high.

6.2.2.210BASE-T Driver and Filter

Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented inside the chip. This allows the two technologies to share the same magnetics. The PHY unit supports both technologies through one pair of TD pins and by externally sharing the same magnetics.

In 10 Mbps mode, the PHY unit begins transmitting the serial Manchester bit stream within 3 bit times (300 nanoseconds) after the MAC asserts TXEN. In 10 Mbps mode the line drivers use a pre- distortion algorithm to improve jitter tolerance. The line drivers reduce their drive level during the second half of “wide” (100ns) Manchester pulses and maintain a full drive level during all narrow (50ns) pulses and the first half of the wide pulses. This reduces line overcharging during wide pulses, a major source of jitter.

6.2.310BASE-T Receive Blocks

6.2.3.110BASE-T Manchester Decoder

The PHY unit performs Manchester decoding and timing recovery when in 10 Mbps mode. The Manchester-encoded data stream is decoded from the RD pair to separate Receive Clock and Receive Data from the differential signal. This data is transferred to the CSMA unit at 2.5 MHz/ nibble. The high-performance circuitry of the PHY unit exceeds the IEEE 802.3 jitter requirements.

6.2.3.210BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter

In 10 Mbps mode, data is expected to be received on the receive differential pair after passing through isolation transformers. The filter is implemented inside the PHY unit for supporting single magnetics that are shared with the 100BASE-TX side. The input differential voltage range for the Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V. The TPE receive buffer distinguishes valid receive data, link test pulses, and the idle condition, according to the requirements of the 10BASE-T standard.

The following line activity is determined to be inactive and is rejected:

Differential pulses of peak magnitude less than 300 mV

Continuous sinusoids with a differential amplitude less than 6.2 Vpp and frequency less than 2 MHz

Sine waves of a single cycle duration starting with 0 or 180° phase that have a differential

amplitude less than 6.2 Vpp and a frequency of at least 2 MHz and not more than 16 MHz. These single-cycle sine waves are discarded only if they are preceded by 4 bit times (400 nanoseconds) of silence.

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Datasheet

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Intel GD82559ER manual 2 10BASE-T Transmit Blocks, 3 10BASE-T Receive Blocks, 2.1 10BASE-T Manchester Encoder

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.