Intel IXF1104 manual 8.4.8MDIO Register Overview, Datasheet

IXF1104 4-Port Gigabit Ethernet Media Access Controller

8.4.8MDIO Register Overview

Table 142 through Table 145 provide an overview of the MDIO registers.

Table 142. MDIO Single Command ($0x680)

Bit	Name	Description	Type1	Default
Register Description: Gives the CPU the ability to perform single MDIO read and write				0x00010000
accesses to the external PHY for ports that are configured in copper mode.
31:21	Reserved	Reserved	RO	00000000000
		Performs the MDIO operation. Cleared when
20	MDIO Command	done.	R/W	0
		0 = MDIO ready, operation complete
		1 = Perform operation
19:18	Reserved	Reserved	RO	00
		MDIO Op Code; two bits identify operation to be
		performed:
		00 = Reserved
17:16	OP Code	01 = Write operation (as defined in IEEE 802.3,	R/W	01
		clause 22.2.4.5)
		10 = Read operation (as defined in IEEE 802.3,
		clause 22.2.4.5)
		11 = Reserved
15:10	Reserved	Reserved	RO	000000
9:8	PHY Address	Sets bits 1:0 of the external PHY address. Bits 4:2	R/W	00
		of the PHY address are fixed at 000.
7:5	Reserved	Reserved	RO	000
4:0	REG Address	Five-bit address to one among 32 registers in an	R/W	00000
		addressed PHY device.

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Table 143. MDIO Single Read and Write Data ($0x681)

Bit	Name	Description	Type1	Default
Register Description: MDIO read and write data.				0x00000000
31:16	MDIO Read Data	MDIO Read data from external device.	RO	0x0000
15:0	MDIO Write Data	MDIO Write data from external device.	R/W	0x0000

1.RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

210 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004