Intel IXF1104 manual 8.4.9SPI3 Register Overview, Datasheet, SPHY/MPHY Mode

Models: IXF1104

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8.4.9SPI3 Register Overview

IXF1104 4-Port Gigabit Ethernet Media Access Controller

8.4.9SPI3 Register Overview

Table 146 through Table 148 “Address Parity Error Packet Drop Counter ($0x70A)” on page 218 provide an overview of the SPI3 registers.

Table 146. SPI3 Transmit and Global Configuration ($0x700) (Sheet 1 of 3)

Bit

Name

Description

Type1

Default

 

 

 

 

 

Register Description: This register gives the configuration related to the SPI3 Transmitter

0x0020000F

and Global configuration (4 x 8 mode).

 

 

 

 

 

 

 

 

31:24

Reserved

Reserved

RO

0x00

 

 

 

 

 

23

SPI3 Transmitter Soft

1 = The SPI3 TX block is reset.

R/W

0

Reset

 

 

 

 

 

 

 

 

 

22

SPI3 Receiver Soft

1 = The SPI3 RX block is reset.

R/W

0

Reset

 

 

 

 

 

 

 

 

 

 

 

0 = Indicates that SPI3 block operates in 32-bit

 

 

 

 

MPHY mode.

 

 

21

SPHY/MPHY Mode

1 = Indicates that the SPI3 block operates in 4 x 8

R/W

1

SPHY mode.

 

 

 

 

 

 

This configuration affects both the SPI3 transmitter

 

 

 

 

and receiver functionality.

 

 

 

 

 

 

 

 

 

Indicates whether to drop packets received with

 

 

 

 

parity error during the address selection phase

 

 

 

 

(Tsx and nTenb High) should be dropped.

 

 

20

Tx_ad_prtyer_drop

0 = Do not drop packets with address parity error

R/W

0

1 = Drop packets with address parity error

 

 

 

 

 

 

This is applicable only in MPHY mode of

 

 

 

 

operation. This bit is ignored in SPHY (4 x 8) mode

 

 

 

 

as there will be no address selection.

 

 

 

 

 

 

 

 

 

SPHY/MPHY Mode:

 

 

 

 

Indicates whether to drop packets with data parity

 

 

19

Dat_prtyer_drp Port 3

error for port 3.

R/W

0x0

0 = Do not drop packets with data parity error

 

 

 

 

 

 

(default)

 

 

 

 

1 = Drop packets with data parity error

 

 

 

 

 

 

 

 

 

SPHY/MPHY Mode:

 

 

 

 

Indicates whether to drop packets with data parity

 

 

18

Dat_prtyer_drp Port 2

error for port 2.

R/W

0

0 = Do not drop packets with data parity error

 

 

 

 

 

 

(default)

 

 

 

 

1 = Drop packets with data parity error

 

 

 

 

 

 

 

 

 

SPHY/MPHY Mode:

 

 

 

 

Indicates whether to drop packets with data parity

 

 

17

Dat_prtyer_drp Port 1

error for port 1.

R/W

0

0 = Do not drop packets with data parity error

 

 

 

 

 

 

(default)

 

 

 

 

1 = Drop packets with data parity error

 

 

 

 

 

 

 

1.RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

212

Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

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Intel IXF1104 manual 8.4.9SPI3 Register Overview, Datasheet, SPHY/MPHY Mode