IXF1104
Note: The LED_DATA signal is now inverted from the state in Mode 0.
Figure 30. Mode 1 Timing
1 | 2 | 3 | 4 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 |
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LED_DATA |
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LED_LATCH |
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Table 33. Mode 1 Clock Cycle to Data Bit Relationship
LED_CLK Cycle | LED_DATA Name | LED_DATA Description | |
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| This bit has no meaning in Mode 1 operation and is shifted out of | |
1 | START BIT | the | |
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| asserted. | |
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| These bits have no meaning in Mode 1 operation and are shifted | |
2:3 | PAD BITS | out of the | |
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| These bits are the actual data to be transmitted to the | |
4:15 | LED DATA | register chain. The decode for each bit in each mode is defined in | |
Table 34 on page 118. | |||
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| The data is INVERTD. Logic 1 (LED ON) = Low. | |
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| These bits have no meaning in Mode 1 operation and are latched | |
36:38 | PAD BITS | into positions 31 and 32 in the shift register chain. These bits are | |
not considered as valid data and should be ignored. They should | |||
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| always be a Logic 0 = High. | |
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5.8.5Power-On, Reset, Initialization
The LED interface is disabled at
5.8.6LED DATA Decodes
The data transmitted on the LED_DATA line is determined by programming the global operation mode as either fiber or copper. Table 34 shows the data decode of the data for both fiber and copper MACs.
Datasheet | 117 |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004