IXF1104
Table 30.
IXF1104 | SFP Signal | Description | Notes | |
Signal Names | Names | |||
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TX_DISABLE_0:3 | TX DISABLE | Transmitter disable, logic High, open | Output from the IXF1104 | |
collector compatible | ||||
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TX_FAULT_0:3 | TX FAULT | Transmitter fault, logic High, open | Input to the IXF1104 | |
collector compatible | ||||
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RX_LOS_0:3 | LOS | Receiver | Input to the IXF1104 | |
open collector compatible | ||||
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5.7.2Functional Descriptions
5.7.2.1High-Speed Serial Interface
These signals are responsible for transfer of the actual data at 1.25 Gbps. Table 41 “Intel® IXF1104 MAC DC Specifications” on page 133 shows the data is 8B/10B encoded and transmitted differentially.
The following signals are required to implement the
•TX_P_0:3
•TX_N_0:3
•RX_P_0:3
•RX_N_0:3
5.7.2.2Low-Speed Status Signaling Interface
The following
•MOD_DEF_0:3
•TX_FAULT_0:3
•RX_LOS_0:3
•TX_DISABLE_0:3
•MOD_DEF_INT
•TX_FAULT_INT
•RX_LOS_INT
5.7.2.2.1MOD_DEF_0:3
MOD_DEF_0:3 are direct inputs to the IXF1104 and are pulled to a logic Low level during normal operation, indicating that a module is present for each channel respectively. If a module is not present, a logic High is received, which is achieved by an external
Datasheet | 107 |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004