IXF1104
Table 90. Diverse Config Write ($ Port_Index + 0x18) (Sheet 2 of 2)
Bit | Name | Description | Type1 | Default |
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3:22 | Reserved | Write as 1, ignore on Read. | R/W | 11 |
12 | Reserved | Write as 0, ignore on Read. | R/W | 0 |
02 | Reserved | Write as 1, ignore on Read. | R/W | 1 |
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
2. Reserved bits must be written to the default value for proper operation.
Table 91. RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 1 of 2)
Bit | Name | Description | Type1 | Default | |
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Register Description: This register allows for specific packet types to be marked for filtering |
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and is used in conjunction with the “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 | 0x00000000 | ||||
- 0x5A5)”. |
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31:6 | Reserved | Reserved |
| 0 | |
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| This bit enables a Global filter on frames with a |
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| CRC Error. |
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| 0 = When CRC Error Pass = 0, all frames with a |
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| CRC Error are marked as bad.2 |
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| 1 = Frames with a CRC Error are not marked as |
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| bad and are passed to the SPI3 interface for |
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| transfer as good frames, regardless of the |
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5 | CRC Error Pass | state of the bits in the “RX FIFO Errored | R/W | 0 | |
Frame Drop Enable ($0x59F)”. | |||||
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| NOTE: When the CRC Error Pass Filter bit = 0, it |
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| takes precedence over the other filter bits. |
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| Any packet, whether is a Pause, Unicast, |
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| Multicast or Broadcast packet with a CRC |
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| error, is marked as a bad frame when |
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| CRC Error Pass = 0 |
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| This bit enables a Global filter on Pause frames. |
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| 0 = All pause frames are dropped.2 |
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| 1 = All pause frames are passed to the SPI3 |
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4 | Pause Frame Pass | Interface. | R/W | 0 | |
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| NOTE: Pause Frames can only be filtered if |
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| RXFD flow control is enabled in the “FC |
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| Enable ($ Port_Index + 0x12)”. |
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| This bit enables a global filter on VLAN frames. |
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3 | VLAN Drop En | 0 = All VLAN frames are passed to the SPI3 | R/W | 0 | |
Interface. | |||||
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| 1 = All VLAN frames are dropped.2 |
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1.RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
2.Used in conjunction with the “RX FIFO Errored Frame Drop Enable ($0x59F)” on page 195. This allows the frame to be dropped in the RX FIFO. Otherwise, the frame is sent out the SP3 interface and may be optionally signaled with an RERR (see bit 0 of “SPI3 Receive Configuration ($0x701)”.
Datasheet | 171 |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
