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Intel IXF1104 manual Datasheet

Models: IXF1104

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IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 98. PHY Identification 2 ($ Port Index + 0x63) (Sheet 2 of 2)

	Bit	Name	Description	Type1	Default

			The PHY identifier is composed of register bits
	15:10	PHY ID Number	24:19 of the OUI (Organizationally Unique	RO	011110
			Identifier)

	9:4	Manufacturer’s Model	Six bits containing the manufacturer’s part number	RO	010000

	3:0	Manufacturer’s	Four bits containing the manufacturer’s revision	RO	0000
	3:0	Revision Number	number	RO	0000
		Revision Number	number

1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write

Table 99. Auto-Negotiation Advertisement ($ Port Index + 0x64) (Sheet 1 of 2)

	Bit	Name	Description	Type1	Default

	31:16	Reserved	Reserved	RO	0

	15	Next Page	0 =	RO	0
	15	Next Page	1 = Manual control of Next Page (software)	RO	0
			1 = Manual control of Next Page (software)

	14	Reserved	Reserved	RO	0

	13	Remote Fault	0 = No remote fault	RO	0
	13	Remote Fault	1 = Remote fault	RO	0
			1 = Remote fault

	12	Reserved	Reserved	RO	0

			Advertise Asymmetric Pause Direction register bit.
			This register bit is used in conjunction with Pause
	11	ASM_DIR	(Register bit 4.10)	RO	1
	11	ASM_DIR	0 = Link partner is not capable of asymmetric	RO	1
			0 = Link partner is not capable of asymmetric
			pause
			1 = Link partner is capable of asymmetric pause

	10	Pause	Advertise to link partner that Pause operation is	RO	0
	10	Pause	desired (IEEE 802.3x Standard)	RO	0
			desired (IEEE 802.3x Standard)

			0 = 100BASE-T4 capability is not available
			1 = 100BASE-T4 capability is available
	9	100BASE-T4	The IXF1104 does not support 100BASE-T4, but	RO	0
	9	100BASE-T4	allows this register bit to be set to advertise in	RO	0
			auto-negotiation sequence for 100BASE-T4
			operation. If this capability is desired, an external
			100BASE-T4 transceiver can be switched in.

			0 = DTE is not 100BASE-TX, full-duplex mode
	8	100BASE-TX	capable	RO	1
	8	Full-Duplex	1 = DTE is 100BASE-TX, full-duplex mode	RO	1
		Full-Duplex	1 = DTE is 100BASE-TX, full-duplex mode
			capable

			0 = DTE is not 100BASE-TX, half-duplex mode
	7	100BASE-TX	capable	RO	1
	7	Half-Duplex	1 = DTE is 100BASE-TX, half-duplex mode	RO	1
		Half-Duplex	1 = DTE is 100BASE-TX, half-duplex mode
			capable

	1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write

Datasheet

183

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Image 183

Intel IXF1104 manual Datasheet

Contents

Datasheet Product FeaturesApplications DatasheetDatasheet ContentsIntroduction ContentsDatasheet ContentsDatasheet ContentsApplications ContentsDatasheet Datasheet Figures10.0 ContentsTables ContentsDatasheet Datasheet ContentsDatasheet ContentsDatasheet ContentsRevision History ContentsDatasheet Revision Date: March 25, ContentsDatasheet Revision Number:Datasheet ContentsSheet 4 of Page # Description ContentsDatasheet Revision Number: Revision Date: March 25,Sheet 5 of ContentsDatasheet Revision Number: Revision Date: March 25,Datasheet ContentsDatasheet ContentsDatasheet 1.0Introduction1.1What You Will Find in This Document 1.2Related DocumentsDatasheet 2.0General DescriptionFigure 2. Internal Architecture Datasheet= No Pad A1 3.0Ball Assignments and Ball List Tables3.1Ball Assignments Datasheet2.SPI3 Ball Connection 3.Fiber Mode Ball Connection3.2Ball List Tables 1.GMII Ball ConnectionDatasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Document Number: Revision Number:Revision Date: March 25, Datasheet 4.0Ball Assignments and Signal Descriptions4.1Naming Conventions 4.1.1Signal Name ConventionsGMII 4.2Interface Signal GroupsDatasheet SPHY MPHYBits 4.3Signal Description TablesDatasheet ModeTransmit Parity DatasheetTransmit Write Enable Transmit Error4 x 8 Single-PHYmode: MOD1:0 is not DatasheetTMOD1:0 Transmit Word Modulo 32-bit Multi-PHYmode: TMOD1:0Datasheet DTPA_0:3 Direct Transmit PacketAvailable Mode DatasheetPolled-PHYTransmit Packet Available Receive Data BusMode DatasheetReceive Read Enable Receive Data Bus4 x 8 Single-PHYmode: The RERR_0:3 DatasheetReceive Error 32-bit Multi-PHYmode: RERR_0 covers4 x 8 Single-PHYmode: The REOP_0:3 DatasheetReceive End of Packet 32-bit Multi-PHYmode: REOP_0 coversDatasheet Table 4. SerDes Interface Signal DescriptionsTransmit Data DatasheetTransmit Enable Transmit ErrorReceive Data Valid DatasheetReceive Error Receive DataTransmit Control DatasheetSource Synchronous Transmit Clock Transmit DataDatasheet Receive DataReceive Control 32-bitmode: Uses 31:0 DatasheetCycle complete indicator Data busDatasheet Transmit DisableReceiver Loss of Signal Interrupt Module Definition Interrupt Table 10. MDIO Interface Signal DescriptionsDatasheet Transmitter Fault InterruptDatasheet Table 11. LED Interface Signal DescriptionsTable 12. JTAG Interface Signal Descriptions Table 13. System Interface Signal DescriptionsDatasheet Table 14. Power Supply Signal Descriptions4.4Ball Usage Summary DatasheetTotal Datasheet 4.5Multiplexed Ball ConnectionsDatasheet 4.5.2SPI3 MPHY/SPHY Ball ConnectionsTable 17. SPI3 MPHY/SPHY Interface Sheet 2 of DatasheetDatasheet 4.6Ball State During ResetDatasheet Datasheet 4.7Power Supply Sequencing4.7.1Power-UpSequence 4.7.2Power-DownSequence4.9Analog Power Filtering 4.8Pull-Up/Pull-DownBall GuidelinesDatasheet Analog Power BallDatasheet 2.5 or 1.85.1Media Access Controller MAC 5.0Functional DescriptionsDatasheet 5.1.1.3Filtering of Receive Packets 5.1.1Features for Fiber and Copper Mode5.1.1.1Padding of Undersized Frames on Transmit 5.1.1.2Automatic CRC Generation5.1.1.3.4Filter VLAN Packets 5.1.1.3.6Filter CRC Error Packets5.1.1.3.2Filter on Multicast Packet Match 5.1.1.3.3Filter Broadcast Packets5.1.1.4CRC Error Detection 5.1.2Flow ControlDatasheet Datasheet 5.1.2.1802.3x Flow Control Full-DuplexOperation5.1.2.1.1Pause Frame Format SPI3 InterfaceDatasheet Datasheet 5.1.2.1.2Pause Settings5.1.2.1.4Half-DuplexOperation 5.1.2.1.5Transmit Pause Control InterfaceDatasheet “FC TX Timer Value $ Port_Index + 0x07 XOFF “FC TX Timer Value $ Port_Index + 0x07 XOFF“FC TX Timer Value $ Port_Index + 0x07 XOFF “FC TX Timer Value $ Port_Index + 0x07 XOFFDatasheet 5.1.3.1Configuration of the IXF11045.1.3.2Key Configuration Registers 5.1.3Mixed-ModeOperationDatasheet 5.1.4Fiber ModeDatasheet 5.1.5Copper Mode5.1.4.3Fiber Forced Mode 5.1.4.1Fiber Auto-Negotiation5.1.5.3Copper Auto-Negotiation 5.1.6Jumbo Packet Support5.1.5.1Speed 5.1.5.2DuplexDatasheet 5.1.6.1Rx Statistics5.1.6.2TX Statistics 5.1.6.3Loss-lessFlow Control5.1.7.1.2RX FIFO 5.1.7Packet Buffer Dimensions5.1.8RMON Statistics Support 5.1.7.1TX and RX FIFO Operation 5.1.7.1.1TX FIFOTable 25. RMON Additional Statistics Sheet 1 of DatasheetDatasheet 5.1.8.1Conventions5.2SPI3 Interface 5.1.8.2IXF1104 AdvantagesDatasheet 5.2.1.1SPI3 RX Round Robin Data Transmission 5.2.1MPHY Operation5.2.2MPHY Logical Timing Data Path5.2.2.1Transmit Timing 5.2.2.2Receive TimingDatasheet Line-SideInterface DatasheetNetwork Processor IXF1104 MPHY5.2.2.5.1Data Path 5.2.2.5SPHY Mode5.2.2.3Clock Rates 5.2.2.4ParityDatasheet 5.2.2.6SPHY Logical Timing5.2.2.7Transmit Timing SPHY 5.2.2.8Receive Timing SPHYFigure 15. SPHY Receive Logical Timing DatasheetDatasheet 5.2.2.8.1Clock Rates5.2.2.9.2TX SPI3 Flow Control 5.2.2.8.2Parity5.2.2.9SPI3 Flow Control 5.2.2.9.1RX SPI3 Flow ControlDatasheet DTPA_0:3STPA PTPA5.3Gigabit Media Independent Interface GMII 5.2.3Pre-PendingFunctionDatasheet 5.3.1GMII Signal Multiplexing 5.3.2GMII Interface Signal DefinitionDatasheet Receive Error DatasheetTransmit Enable Transmit ErrorQuad PHY Device Media Access Controller5.4.1Multiplexing of Data and Control Intel IXF11045.4.2Timing Specifics 5.4.3TX_ER and RX_ER CodingDatasheet TX_CTL_0:3 DatasheetTXC_0:3 TD3:0_0:3Datasheet 5.5MDIO Control and Interface5.4.410/100 Mbps Functionality 5.4.3.1In-BandStatus5.5.4MDC Generation 5.5.3Clear When Done5.5.1MDIO Address 5.5.2MDIO Register DescriptionsDatasheet 5.5.6Single MDI Command Operation5.5.5Management Frames 5.5.7MDI State MachineFigure 22. MDI State Datasheet5.6.2Functional Description 5.6.1Features5.6SerDes Interface 5.5.8Autoscan OperationDatasheet 5.6.2.1Transmitter Operational OverviewDatasheet 5.6.2.4Selective Power-Down5.6.2.3Receiver Operational Overview 5.6.2.5Receiver Jitter ToleranceSinusoidal Jitter Mask 5.6.2.6Transmit Jitter5.6.2.7Receive Jitter DatasheetDatasheet 5.7Optical Module Interface5.7.2.2.1MOD_DEF_0:3 5.7.2.2Low-SpeedStatus Signaling Interface5.7.2Functional Descriptions 5.7.2.1High-SpeedSerial Interface5.7.2.2.3RX_LOS_0:3 5.7.2.2.2TX_FAULT_0:35.7.2.2.4TX_DISABLE_0:3 5.7.2.2.6TX_FAULT_INT•“I2C Control Ports 0 - 3 $0x79B” on page 5.7.3I²C Module Configuration Interface5.7.3.1I2C Control and Data Registers 5.7.3.2I2C Read OperationDatasheet 5.7.3.3I2C Write OperationDatasheet 5.7.3.4I²C Protocol Specifics5.7.3.5Port Protocol Operation 5.7.3.6Clock and Data TransitionsDatasheet 5.7.3.6.1Start Condition5.7.3.6.2Stop Condition 5.7.3.6.3AcknowledgeDatasheet 5.7.3.6.4Memory Reset5.7.3.6.5Device Addressing 5.7.3.6.6Random Read OperationDatasheet 5.8.2LED Interface Signal Description5.8LED Interface 5.8.1Modes of OperationDatasheet 5.8.3Mode 0: Detailed OperationDatasheet 5.8.4Mode 1: Detailed Operation5.8.5Power-On,Reset, Initialization 5.8.6LED DATA DecodesDatasheet 5.8.6.1LED Signaling Behavior 5.8.6.1.1 Fiber LED BehaviorDatasheet 5.9CPU Interface 5.8.6.1.2Copper LED BehaviorDatasheet Datasheet 5.9.1.1Read Access5.9.1.2Write Access 5.9.1Functional Description5.9.2Endian 5.9.1.3CPU Timing ParametersDatasheet 5.10TAP Interface JTAG 5.10.1TAP State MachineDatasheet Table 38. Instruction Register Description Datasheet5.10.5Bypass Register 5.11Loopback Modes5.10.3ID Register 5.10.4Boundary Scan RegisterDatasheet 5.11.2Line Side Interface Loopback5.12Clocks 5.12.1System Interface Reference ClocksDatasheet 5.12.1.1CLK125 5.12.2SPI3 Receive and Transmit Clocks5.12.3RGMII Clocks 5.12.4MDC ClockDatasheet 5.12.5JTAG Clock5.12.6I2C Clock 5.12.7LED Clock6.1Change Port Mode Initialization Sequence 6.0ApplicationsDatasheet Datasheet 13.Assert set to 1 “Port Enable $0x500”Datasheet 7.0Electrical SpecificationsDatasheet 7.1DC SpecificationsDatasheet Table 41. Intel IXF1104 MAC DC Specifications7.1.1Undershoot / Overshoot Specifications 7.1.2RGMII Electrical CharacteristicsDatasheet Datasheet Table 45. RGMII Power7.2SPI3 AC Timing Specifications 7.2.1Receive Interface TimingDatasheet Datasheet Datasheet 7.2.2Transmit Interface TimingDatasheet Datasheet 7.3RGMII AC Timing SpecificationDatasheet 7.4GMII AC Timing Specification7.4.11000 Base-TOperation 7.4.1.11000 BASE-TTransmit InterfaceDatasheet 7.4.1.21000BASE-TReceive InterfaceDatasheet 7.5SerDes AC Timing SpecificationDatasheet 7.6MDIO AC Timing Specification7.6.1MDC High-SpeedOperation Timing 7.6.2MDC Low-SpeedOperation TimingMDC MDIO 7.6.3MDIO AC TimingDatasheet MDIO7.7Optical Module and I2C AC Timing Specification 7.7.1I2C Interface TimingDatasheet Datasheet Datasheet 7.8CPU AC Timing Specification7.8.1CPU Interface Read Cycle AC Timing 7.8.2CPU Interface Write Cycle AC TimingDatasheet Datasheet 7.9Transmit Pause Control AC Timing SpecificationDatasheet 7.10JTAG AC Timing SpecificationDatasheet 7.11System AC Timing SpecificationDatasheet 7.12LED AC Timing SpecificationDatasheet 8.0Register Set8.1Document Structure 8.2Graphical Representation8.3Per Port Registers 8.4Register MapDatasheet Datasheet Datasheet Datasheet Datasheet Datasheet Table 68. SerDes Registers $ 0x780 - DatasheetSource MAC address bit 8.4.1MAC Control RegistersDatasheet Source MAC address bitTable 74. Collision Threshold $ Port_Index + Table 75. FC TX Timer Value $ Port_Index +Datasheet Table 73. Collision Distance $ Port_Index +Table 79. IPG Transmit Time $ Port_Index + 0x0C DatasheetTable 77. IPG Receive Time 1 $ Port_Index + 0x0A Table 78. IPG Receive Time 2 $ Port_Index + 0x0BDatasheet Table 80. Pause Threshold $ Port_Index + 0x0ETable 81. Max Frame Size Addr: Port_Index + 0x0F Table 83. Flush TX $ Port_Index + DatasheetTable 84. FC Enable $ Port_Index + DatasheetTable 85. FC Back Pressure Length $ Port_Index + Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet 8.4.2MAC RX Statistics Register OverviewDatasheet Datasheet Datasheet Datasheet 8.4.3MAC TX Statistics Register OverviewDatasheet Datasheet Datasheet 8.4.4PHY Autoscan RegistersDatasheet Datasheet Datasheet Datasheet Datasheet Datasheet Table 103. Port Enable $0x500 Table 104. Interface Mode $0x501Datasheet Table 105. Link LED Enable $0x502 Table 106. MAC Soft Reset $0x505Datasheet Table 109. LED Control $0x509 Table 107. MDIO Soft Reset $0x506Datasheet Table 108. CPU Interface $0x508Table 111. LED Fault Disable $0x50B DatasheetTable 110. LED Flash Rate $0x50A Table 112. JTAG ID $0x50C DatasheetDatasheet 8.4.6RX FIFO Register OverviewTable 118. RX FIFO Low Watermark Port 1 $0x58B DatasheetTable 116. RX FIFO High Watermark Port 3 $0x583 Table 117. RX FIFO Low Watermark Port 0 $0x58ADatasheet Table 119. RX FIFO Low Watermark Port 2 $0x58CTable 120. RX FIFO Low Watermark Port 3 $0x58D Datasheet Table 122. RX FIFO Port Reset $0x59ETable 124. RX FIFO Overflow Event $0x5A0 Datasheet0x19” with the“RX FIFO Errored FrameDrop Enable $0x59F” and the “RX Packet Filter Control $ Port_Index +Drop Enable $0x59F” and the “RX with the“RX FIFO Errored FrameDrop Enable $0x59F” and the “RX with the“RX FIFO Errored FrameDatasheet Datasheet Datasheet High watermark for TX FIFO Port 1. The 8.4.7TX FIFO Register OverviewDatasheet High watermark for TX FIFO Port 0. TheLow watermark for TX FIFO Port 2. The DatasheetLow watermark for TX FIFO Port 0. The Low watermark for TX FIFO Port 1. TheMAC threshold for TX FIFO Port 2. The DatasheetMAC threshold for TX FIFO Port 0. The MAC threshold for TX FIFO Port 1. TheDatasheet Register Description: TX FIFO Underflow EventRegister Description: TX FIFO Overflow Event Datasheet Datasheet Table 137. TX FIFO Port Reset $0x620 Sheet 2 ofDatasheet Datasheet Table 141. TX FIFO Port Drop Enable $0x63DDatasheet 8.4.8MDIO Register OverviewTable 144. Autoscan PHY Address Enable $0x682 DatasheetTable 145. MDIO Control $0x683 SPHY/MPHY Mode 8.4.9SPI3 Register OverviewDatasheet SPHY/MPHY ModeMPHY Mode DatasheetSPHY/MPHY Mode SPHY ModeSPHY Mode DatasheetSPHY Mode MPHY ModeSPHY Mode DatasheetSPHY Mode MPHY ModeSPHY Mode DatasheetSPHY Mode MPHY ModeSPHY Mode DatasheetSPHY Mode MPHY ModeDatasheet Datasheet 8.4.10SerDes Register OverviewDatasheet Datasheet 8.4.11Optical Module Register OverviewDatasheet Table 155. I2C Control Ports 0 - 3 $0x79BTable 156. I2C Data Ports 0 - 3 $0x79F 9.2Package Specifics for the IXF1104 9.0Mechanical Specifications9.1.1Features 9.1Overview= No ball 9.3Package InformationDatasheet = BallDatasheet Figure 56. CBGA Package Side View DiagramPin 1 mark Syww9001 Country 9.3.1Example Package MarkingDatasheet Syww900110.0Product Ordering Information DatasheetTray