IXF1104
Table 139. TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)
Name | Description | Address | Type* | Default | |
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|
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| |
| This register provides the number of packets |
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| |
| dropped by the TX FIFO due to the following: |
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|
| |
| Data Parity Errors |
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|
| |
TX FIFO errored | Short SOPs (two consecutive SOPs for a port |
|
|
| |
with no EOP) |
|
|
| ||
frame drop counter | 0x625 | R | 0x00000000 | ||
Small Packets | |||||
on Port 0 |
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|
| ||
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|
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| ||
| Frames received that are signaled with TERR |
|
|
| |
| on the SPI3 TX interface. |
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|
| |
| NOTE: This register is cleared on Read. |
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|
| |
|
|
|
|
| |
| This register provides the number of packets |
|
|
| |
| dropped by the TX FIFO due to the following: |
|
|
| |
| Data Parity Errors |
|
|
| |
TX FIFO errored | Short SOPs (two consecutive SOPs for a port |
|
|
| |
with no EOP) |
|
|
| ||
frame drop counter | 0x626 | R | 0x00000000 | ||
Small Packets | |||||
on Port 1 |
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|
| ||
Frames received that are signaled with TERR |
|
|
| ||
|
|
|
| ||
| on the SPI3 TX interface. |
|
|
| |
| NOTE: This register is cleared on Read. |
|
|
| |
|
|
|
|
| |
| This register provides the number of packets |
|
|
| |
| dropped by the TX FIFO due to the following: |
|
|
| |
| Data Parity Errors |
|
|
| |
TX FIFO errored | Short SOPs (two consecutive SOPs for a port |
|
|
| |
with no EOP) |
|
|
| ||
frame drop counter | 0x627 | R | 0x00000000 | ||
Small Packets | |||||
on Port 2 |
|
|
| ||
|
|
|
| ||
| Frames received that are signaled with TERR |
|
|
| |
| on the SPI3 TX interface. |
|
|
| |
| NOTE: This register is cleared on Read. |
|
|
| |
|
|
|
|
| |
| This register provides the number of packets |
|
|
| |
| dropped by the TX FIFO due to the following: |
|
|
| |
| Data Parity Errors |
|
|
| |
TX FIFO errored | Short SOPs (two consecutive SOPs for a port |
|
|
| |
with no EOP) |
|
|
| ||
frame drop counter | 0x628 | R | 0x00000000 | ||
Small Packets | |||||
on Port 3 |
|
|
| ||
Frames received that are signaled with TERR |
|
|
| ||
|
|
|
| ||
| on the SPI3 TX interface. |
|
|
| |
| NOTE: This register is cleared on Read. |
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1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
208 | Datasheet |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004