Intel IXF1104 manual SPI3 MPHY/SPHY Interface Sheet 2 of, Datasheet

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 17. SPI3 MPHY/SPHY Interface (Sheet 2 of 3)

SPI3 Signals			Ball Number			Comments
MPHY	SPHY
TERR_0	TERR_0	A8				MPHY: Use TERR_0 as the TERR
GND	TERR_1	K1
						signal.
						SPHY: Each port has its own dedicated
GND	TERR_2	E11
						TERR_n signal
GND	TERR_3	J8
TSOP_0	TSOP_0	C7				MPHY: Use TSOP_0 as the TSOP
GND	TSOP_1	E3
						signal.
						SPHY: Each port has a dedicated
GND	TSOP_2	C10
						TSOP_n signal.
GND	TSOP_3	J5
TEOP_0	TEOP_0	A7				MPHY: Use TEOP_0 as the TEOP
GND	TEOP_1	F3
						signal.
						SPHY: Each port has a dedicated
GND	TEOP_2	E4
						TEOP_n signal.
GND	TEOP_3	H5
TMOD[1:0]	GND	D9	A6			TSX and TMOD[1:0] are only applicable
TSX	GND	E1				in MPHY mode.
TADR[1:0]	TADR[1:0]	A12	A11			Used to address port for PTPA signal.
PTPA	PTPA	B11				PTPA can be used in MPHY and SPHY
						modes.
DTPA_0:3	DTPA_0:3	D3	L1	A9	J7	DTPA is available on a per-port basis in
						both MPHY and SPHY modes.
STPA	NC	C11				STPA is only applicable in MPHY mode.
RDAT[31:24]	RDAT[7:0]_3	F24	G24	G23	G22
		G21	G20	G19	G18
RDAT[23:16]	RDAT[7:0]_2	E21	E22	D22	C22	MPHY: Consists of a single 32 bit data
		C21	C20	B22	B20	bus.
						SPHY: Separate 8-bit data bus for each
RDAT[15:8]	RDAT[7:0]_1	F18	E18	E17	F16
		E16	D16	C17	A17	Ethernet port.
RDAT[7:0]	RDAT[7:0]_0	F14	E14	D14	C13
		C14	B14	A15	A14,
						To achieve maximum bandwidth, set
RFCLK	RFCLK	A19				RFCLK as follows:
						MPHY: 133 Mhz.
						SPHY: 125 Mhz.
RPRTY_0	RPRTY_0	E15				MPHY: Use RPRTY_0 as the RPRTY
NC	RPRTY_1	G16
						signal.
						SPHY: Each port has a dedicated
NC	RPRTY_2	E20
						RPRTY_n signal.
NC	RPRTY_3	F20
RENB_0	RENB_0	A13				MPHY: Use RENB_0 as the RENB
VDD2	RENB_1	A18
						signal.
						SPHY: Each port has a dedicated
VDD2	RENB_2	C19
						RENB_n signal
VDD2	RENB_3	E24

Datasheet 59

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004