Intel IXF1104 manual Internal Architecture, Datasheet

Models: IXF1104

Figure 2. Internal Architecture

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IXF1104 4-Port Gigabit Ethernet Media Access Controller

Figure 2 illustrates the IXF1104 internal architecture.

CPU Interface

RMON Statistics

CPU Interface

RMON Statistics

Packet

Buffer

10/100/1000 MAC

RGMII/GMII Interface

PMA Layer		SerDes

RGMII/GMII Interface

Packet

Buffer

10/100/1000 MAC

PMA Layer

SerDes

SPI3 Interface

TXPacket

RXBuffer

TXPacket

RXBuffer

Clock Control Block

Clock Register Block

PLLs

MDIO

10/100/1000 MAC

OMI

RGMII/GMII Interface


PMA Layer		SerDes

RGMII/GMII Interface


PMA Layer		SerDes

B3176-01

Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Page 21

Image 21

Intel IXF1104 manual Internal Architecture, Datasheet

Contents

Datasheet Product FeaturesApplications DatasheetIntroduction ContentsContents DatasheetDatasheet ContentsDatasheet ContentsApplications ContentsDatasheet 10.0 FiguresContents DatasheetTables ContentsDatasheet Datasheet ContentsDatasheet ContentsDatasheet ContentsRevision History ContentsDatasheet Datasheet ContentsRevision Number: Revision Date: March 25,Datasheet ContentsDatasheet ContentsRevision Number: Revision Date: March 25, Sheet 4 of Page # DescriptionDatasheet ContentsRevision Number: Revision Date: March 25, Sheet 5 ofDatasheet ContentsDatasheet Contents1.1What You Will Find in This Document 1.0Introduction1.2Related Documents DatasheetDatasheet 2.0General DescriptionFigure 2. Internal Architecture Datasheet3.1Ball Assignments 3.0Ball Assignments and Ball List TablesDatasheet = No Pad A13.2Ball List Tables 3.Fiber Mode Ball Connection1.GMII Ball Connection 2.SPI3 Ball ConnectionDatasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Document Number: Revision Number:Revision Date: March 25, 4.1Naming Conventions 4.0Ball Assignments and Signal Descriptions4.1.1Signal Name Conventions DatasheetDatasheet 4.2Interface Signal GroupsSPHY MPHY GMIIDatasheet 4.3Signal Description TablesMode BitsTransmit Write Enable DatasheetTransmit Error Transmit ParityTMOD1:0 Transmit Word Modulo Datasheet32-bit Multi-PHYmode: TMOD1:0 4 x 8 Single-PHYmode: MOD1:0 is notDatasheet DTPA_0:3 Direct Transmit PacketAvailable Polled-PHYTransmit Packet Available DatasheetReceive Data Bus ModeReceive Read Enable DatasheetReceive Data Bus ModeReceive Error Datasheet32-bit Multi-PHYmode: RERR_0 covers 4 x 8 Single-PHYmode: The RERR_0:3Receive End of Packet Datasheet32-bit Multi-PHYmode: REOP_0 covers 4 x 8 Single-PHYmode: The REOP_0:3Datasheet Table 4. SerDes Interface Signal DescriptionsTransmit Enable DatasheetTransmit Error Transmit DataReceive Error DatasheetReceive Data Receive Data ValidSource Synchronous Transmit Clock DatasheetTransmit Data Transmit ControlDatasheet Receive DataReceive Control Cycle complete indicator DatasheetData bus 32-bitmode: Uses 31:0Datasheet Transmit DisableReceiver Loss of Signal Interrupt Datasheet Table 10. MDIO Interface Signal DescriptionsTransmitter Fault Interrupt Module Definition InterruptTable 12. JTAG Interface Signal Descriptions Table 11. LED Interface Signal DescriptionsTable 13. System Interface Signal Descriptions DatasheetDatasheet Table 14. Power Supply Signal Descriptions4.4Ball Usage Summary DatasheetTotal Datasheet 4.5Multiplexed Ball ConnectionsDatasheet 4.5.2SPI3 MPHY/SPHY Ball ConnectionsTable 17. SPI3 MPHY/SPHY Interface Sheet 2 of DatasheetDatasheet 4.6Ball State During ResetDatasheet 4.7.1Power-UpSequence 4.7Power Supply Sequencing4.7.2Power-DownSequence Datasheet4.9Analog Power Filtering 4.8Pull-Up/Pull-DownBall GuidelinesDatasheet Datasheet Power Ball2.5 or 1.8 Analog5.1Media Access Controller MAC 5.0Functional DescriptionsDatasheet 5.1.1.1Padding of Undersized Frames on Transmit 5.1.1Features for Fiber and Copper Mode5.1.1.2Automatic CRC Generation 5.1.1.3Filtering of Receive Packets5.1.1.3.2Filter on Multicast Packet Match 5.1.1.3.6Filter CRC Error Packets5.1.1.3.3Filter Broadcast Packets 5.1.1.3.4Filter VLAN Packets5.1.1.4CRC Error Detection 5.1.2Flow ControlDatasheet Datasheet 5.1.2.1802.3x Flow Control Full-DuplexOperation5.1.2.1.1Pause Frame Format SPI3 InterfaceDatasheet Datasheet 5.1.2.1.2Pause Settings5.1.2.1.4Half-DuplexOperation 5.1.2.1.5Transmit Pause Control InterfaceDatasheet “FC TX Timer Value $ Port_Index + 0x07 XOFF “FC TX Timer Value $ Port_Index + 0x07 XOFF“FC TX Timer Value $ Port_Index + 0x07 XOFF “FC TX Timer Value $ Port_Index + 0x07 XOFF5.1.3.2Key Configuration Registers 5.1.3.1Configuration of the IXF11045.1.3Mixed-ModeOperation DatasheetDatasheet 5.1.4Fiber Mode5.1.4.3Fiber Forced Mode 5.1.5Copper Mode5.1.4.1Fiber Auto-Negotiation Datasheet5.1.5.1Speed 5.1.6Jumbo Packet Support5.1.5.2Duplex 5.1.5.3Copper Auto-Negotiation5.1.6.2TX Statistics 5.1.6.1Rx Statistics5.1.6.3Loss-lessFlow Control Datasheet5.1.8RMON Statistics Support 5.1.7Packet Buffer Dimensions5.1.7.1TX and RX FIFO Operation 5.1.7.1.1TX FIFO 5.1.7.1.2RX FIFOTable 25. RMON Additional Statistics Sheet 1 of DatasheetDatasheet 5.1.8.1Conventions5.2SPI3 Interface 5.1.8.2IXF1104 AdvantagesDatasheet 5.2.2MPHY Logical Timing 5.2.1MPHY OperationData Path 5.2.1.1SPI3 RX Round Robin Data Transmission5.2.2.1Transmit Timing 5.2.2.2Receive TimingDatasheet Network Processor DatasheetIXF1104 MPHY Line-SideInterface5.2.2.3Clock Rates 5.2.2.5SPHY Mode5.2.2.4Parity 5.2.2.5.1Data Path5.2.2.7Transmit Timing SPHY 5.2.2.6SPHY Logical Timing5.2.2.8Receive Timing SPHY DatasheetFigure 15. SPHY Receive Logical Timing DatasheetDatasheet 5.2.2.8.1Clock Rates5.2.2.9SPI3 Flow Control 5.2.2.8.2Parity5.2.2.9.1RX SPI3 Flow Control 5.2.2.9.2TX SPI3 Flow ControlSTPA DTPA_0:3PTPA Datasheet5.3Gigabit Media Independent Interface GMII 5.2.3Pre-PendingFunctionDatasheet 5.3.1GMII Signal Multiplexing 5.3.2GMII Interface Signal DefinitionDatasheet Transmit Enable DatasheetTransmit Error Receive Error5.4.1Multiplexing of Data and Control Media Access ControllerIntel IXF1104 Quad PHY Device5.4.2Timing Specifics 5.4.3TX_ER and RX_ER CodingDatasheet TXC_0:3 DatasheetTD3:0_0:3 TX_CTL_0:35.4.410/100 Mbps Functionality 5.5MDIO Control and Interface5.4.3.1In-BandStatus Datasheet5.5.1MDIO Address 5.5.3Clear When Done5.5.2MDIO Register Descriptions 5.5.4MDC Generation5.5.5Management Frames 5.5.6Single MDI Command Operation5.5.7MDI State Machine DatasheetFigure 22. MDI State Datasheet5.6SerDes Interface 5.6.1Features5.5.8Autoscan Operation 5.6.2Functional DescriptionDatasheet 5.6.2.1Transmitter Operational Overview5.6.2.3Receiver Operational Overview 5.6.2.4Selective Power-Down5.6.2.5Receiver Jitter Tolerance Datasheet5.6.2.7Receive Jitter 5.6.2.6Transmit JitterDatasheet Sinusoidal Jitter MaskDatasheet 5.7Optical Module Interface5.7.2Functional Descriptions 5.7.2.2Low-SpeedStatus Signaling Interface5.7.2.1High-SpeedSerial Interface 5.7.2.2.1MOD_DEF_0:35.7.2.2.4TX_DISABLE_0:3 5.7.2.2.2TX_FAULT_0:35.7.2.2.6TX_FAULT_INT 5.7.2.2.3RX_LOS_0:35.7.3.1I2C Control and Data Registers 5.7.3I²C Module Configuration Interface5.7.3.2I2C Read Operation •“I2C Control Ports 0 - 3 $0x79B” on pageDatasheet 5.7.3.3I2C Write Operation5.7.3.5Port Protocol Operation 5.7.3.4I²C Protocol Specifics5.7.3.6Clock and Data Transitions Datasheet5.7.3.6.2Stop Condition 5.7.3.6.1Start Condition5.7.3.6.3Acknowledge Datasheet5.7.3.6.5Device Addressing 5.7.3.6.4Memory Reset5.7.3.6.6Random Read Operation Datasheet5.8LED Interface 5.8.2LED Interface Signal Description5.8.1Modes of Operation DatasheetDatasheet 5.8.3Mode 0: Detailed OperationDatasheet 5.8.4Mode 1: Detailed Operation5.8.5Power-On,Reset, Initialization 5.8.6LED DATA DecodesDatasheet 5.8.6.1LED Signaling Behavior 5.8.6.1.1 Fiber LED BehaviorDatasheet 5.9CPU Interface 5.8.6.1.2Copper LED BehaviorDatasheet 5.9.1.2Write Access 5.9.1.1Read Access5.9.1Functional Description Datasheet5.9.2Endian 5.9.1.3CPU Timing ParametersDatasheet 5.10TAP Interface JTAG 5.10.1TAP State MachineDatasheet Table 38. Instruction Register Description Datasheet5.10.3ID Register 5.11Loopback Modes5.10.4Boundary Scan Register 5.10.5Bypass RegisterDatasheet 5.11.2Line Side Interface Loopback5.12Clocks 5.12.1System Interface Reference ClocksDatasheet 5.12.3RGMII Clocks 5.12.2SPI3 Receive and Transmit Clocks5.12.4MDC Clock 5.12.1.1CLK1255.12.6I2C Clock 5.12.5JTAG Clock5.12.7LED Clock Datasheet6.1Change Port Mode Initialization Sequence 6.0ApplicationsDatasheet Datasheet 13.Assert set to 1 “Port Enable $0x500”Datasheet 7.0Electrical SpecificationsDatasheet 7.1DC SpecificationsDatasheet Table 41. Intel IXF1104 MAC DC Specifications7.1.1Undershoot / Overshoot Specifications 7.1.2RGMII Electrical CharacteristicsDatasheet Datasheet Table 45. RGMII Power7.2SPI3 AC Timing Specifications 7.2.1Receive Interface TimingDatasheet Datasheet Datasheet 7.2.2Transmit Interface TimingDatasheet Datasheet 7.3RGMII AC Timing Specification7.4.11000 Base-TOperation 7.4GMII AC Timing Specification7.4.1.11000 BASE-TTransmit Interface DatasheetDatasheet 7.4.1.21000BASE-TReceive InterfaceDatasheet 7.5SerDes AC Timing Specification7.6.1MDC High-SpeedOperation Timing 7.6MDIO AC Timing Specification7.6.2MDC Low-SpeedOperation Timing DatasheetDatasheet 7.6.3MDIO AC TimingMDIO MDC MDIO7.7Optical Module and I2C AC Timing Specification 7.7.1I2C Interface TimingDatasheet Datasheet 7.8.1CPU Interface Read Cycle AC Timing 7.8CPU AC Timing Specification7.8.2CPU Interface Write Cycle AC Timing DatasheetDatasheet Datasheet 7.9Transmit Pause Control AC Timing SpecificationDatasheet 7.10JTAG AC Timing SpecificationDatasheet 7.11System AC Timing SpecificationDatasheet 7.12LED AC Timing Specification8.1Document Structure 8.0Register Set8.2Graphical Representation Datasheet8.3Per Port Registers 8.4Register MapDatasheet Datasheet Datasheet Datasheet Datasheet Datasheet Table 68. SerDes Registers $ 0x780 - DatasheetDatasheet 8.4.1MAC Control RegistersSource MAC address bit Source MAC address bitDatasheet Table 75. FC TX Timer Value $ Port_Index +Table 73. Collision Distance $ Port_Index + Table 74. Collision Threshold $ Port_Index +Table 77. IPG Receive Time 1 $ Port_Index + 0x0A DatasheetTable 78. IPG Receive Time 2 $ Port_Index + 0x0B Table 79. IPG Transmit Time $ Port_Index + 0x0CDatasheet Table 80. Pause Threshold $ Port_Index + 0x0ETable 81. Max Frame Size Addr: Port_Index + 0x0F Table 83. Flush TX $ Port_Index + DatasheetTable 84. FC Enable $ Port_Index + DatasheetTable 85. FC Back Pressure Length $ Port_Index + Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet 8.4.2MAC RX Statistics Register OverviewDatasheet Datasheet Datasheet Datasheet 8.4.3MAC TX Statistics Register OverviewDatasheet Datasheet Datasheet 8.4.4PHY Autoscan RegistersDatasheet Datasheet Datasheet Datasheet Datasheet Datasheet Table 103. Port Enable $0x500 Table 104. Interface Mode $0x501Datasheet Table 105. Link LED Enable $0x502 Table 106. MAC Soft Reset $0x505Datasheet Datasheet Table 107. MDIO Soft Reset $0x506Table 108. CPU Interface $0x508 Table 109. LED Control $0x509Table 111. LED Fault Disable $0x50B DatasheetTable 110. LED Flash Rate $0x50A Table 112. JTAG ID $0x50C DatasheetDatasheet 8.4.6RX FIFO Register OverviewTable 116. RX FIFO High Watermark Port 3 $0x583 DatasheetTable 117. RX FIFO Low Watermark Port 0 $0x58A Table 118. RX FIFO Low Watermark Port 1 $0x58BDatasheet Table 119. RX FIFO Low Watermark Port 2 $0x58CTable 120. RX FIFO Low Watermark Port 3 $0x58D Datasheet Table 122. RX FIFO Port Reset $0x59ETable 124. RX FIFO Overflow Event $0x5A0 DatasheetDrop Enable $0x59F” and the “RX with the“RX FIFO Errored FramePacket Filter Control $ Port_Index + 0x19”Drop Enable $0x59F” and the “RX with the“RX FIFO Errored Framewith the“RX FIFO Errored Frame Drop Enable $0x59F” and the “RXDatasheet Datasheet Datasheet Datasheet 8.4.7TX FIFO Register OverviewHigh watermark for TX FIFO Port 0. The High watermark for TX FIFO Port 1. TheLow watermark for TX FIFO Port 0. The DatasheetLow watermark for TX FIFO Port 1. The Low watermark for TX FIFO Port 2. TheMAC threshold for TX FIFO Port 0. The DatasheetMAC threshold for TX FIFO Port 1. The MAC threshold for TX FIFO Port 2. TheDatasheet Register Description: TX FIFO Underflow EventRegister Description: TX FIFO Overflow Event Datasheet Datasheet Table 137. TX FIFO Port Reset $0x620 Sheet 2 ofDatasheet Datasheet Table 141. TX FIFO Port Drop Enable $0x63DDatasheet 8.4.8MDIO Register OverviewTable 144. Autoscan PHY Address Enable $0x682 DatasheetTable 145. MDIO Control $0x683 Datasheet 8.4.9SPI3 Register OverviewSPHY/MPHY Mode SPHY/MPHY ModeSPHY/MPHY Mode DatasheetSPHY Mode MPHY ModeSPHY Mode DatasheetMPHY Mode SPHY ModeSPHY Mode DatasheetMPHY Mode SPHY ModeSPHY Mode DatasheetMPHY Mode SPHY ModeSPHY Mode DatasheetMPHY Mode SPHY ModeDatasheet Datasheet 8.4.10SerDes Register OverviewDatasheet Datasheet 8.4.11Optical Module Register OverviewDatasheet Table 155. I2C Control Ports 0 - 3 $0x79BTable 156. I2C Data Ports 0 - 3 $0x79F 9.1.1Features 9.0Mechanical Specifications9.1Overview 9.2Package Specifics for the IXF1104Datasheet 9.3Package Information= Ball = No ballDatasheet Figure 56. CBGA Package Side View DiagramDatasheet 9.3.1Example Package MarkingSyww9001 Pin 1 mark Syww9001 Country10.0Product Ordering Information DatasheetTray