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IXF1104 manual Contents, Datasheet
Models:
IXF1104
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Specification
7.1.2RGMII Electrical Characteristics
CBGA Package Side View Diagram
Datasheet
Dimension
5.1.3.1Configuration of the IXF1104
4.6Ball State During Reset
5.5.6Single MDI Command Operation
Transmit Error
“FC TX Timer Value $ Port_Index + 0x07 XOFF
Page 18
Image 18
Contents
18
Datasheet
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
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Contents
Product Features
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Applications
Contents
Contents
Introduction
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Contents
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Contents
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Applications
Contents
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Contents
Figures
10.0
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Tables
Contents
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Contents
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Contents
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Contents
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Revision History
Contents
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Revision Number:
Contents
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Revision Date: March 25,
Contents
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Revision Number: Revision Date: March 25,
Contents
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Sheet 4 of Page # Description
Revision Number: Revision Date: March 25,
Contents
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Sheet 5 of
Contents
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Contents
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1.2Related Documents
1.0Introduction
1.1What You Will Find in This Document
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2.0General Description
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Figure 2. Internal Architecture
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3.0Ball Assignments and Ball List Tables
3.1Ball Assignments
= No Pad A1
1.GMII Ball Connection
3.Fiber Mode Ball Connection
3.2Ball List Tables
2.SPI3 Ball Connection
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Document Number: Revision Number:
Revision Date: March 25,
4.1.1Signal Name Conventions
4.0Ball Assignments and Signal Descriptions
4.1Naming Conventions
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SPHY MPHY
4.2Interface Signal Groups
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GMII
Mode
4.3Signal Description Tables
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Bits
Transmit Error
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Transmit Write Enable
Transmit Parity
32-bit Multi-PHYmode: TMOD1:0
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TMOD1:0 Transmit Word Modulo
4 x 8 Single-PHYmode: MOD1:0 is not
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DTPA_0:3 Direct Transmit Packet
Available
Receive Data Bus
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Polled-PHYTransmit Packet Available
Mode
Receive Data Bus
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Receive Read Enable
Mode
32-bit Multi-PHYmode: RERR_0 covers
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Receive Error
4 x 8 Single-PHYmode: The RERR_0:3
32-bit Multi-PHYmode: REOP_0 covers
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Receive End of Packet
4 x 8 Single-PHYmode: The REOP_0:3
Table 4. SerDes Interface Signal Descriptions
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Transmit Error
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Transmit Enable
Transmit Data
Receive Data
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Receive Error
Receive Data Valid
Transmit Data
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Source Synchronous Transmit Clock
Transmit Control
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Receive Data
Receive Control
Data bus
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Cycle complete indicator
32-bitmode: Uses 31:0
Datasheet
Transmit Disable
Receiver Loss of Signal Interrupt
Transmitter Fault Interrupt
Table 10. MDIO Interface Signal Descriptions
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Module Definition Interrupt
Table 13. System Interface Signal Descriptions
Table 11. LED Interface Signal Descriptions
Table 12. JTAG Interface Signal Descriptions
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Table 14. Power Supply Signal Descriptions
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4.4Ball Usage Summary
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Total
4.5Multiplexed Ball Connections
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4.5.2SPI3 MPHY/SPHY Ball Connections
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Table 17. SPI3 MPHY/SPHY Interface Sheet 2 of
4.6Ball State During Reset
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4.7.2Power-DownSequence
4.7Power Supply Sequencing
4.7.1Power-UpSequence
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4.9Analog Power Filtering
4.8Pull-Up/Pull-DownBall Guidelines
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2.5 or 1.8
Power Ball
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Analog
5.1Media Access Controller MAC
5.0Functional Descriptions
Datasheet
5.1.1.2Automatic CRC Generation
5.1.1Features for Fiber and Copper Mode
5.1.1.1Padding of Undersized Frames on Transmit
5.1.1.3Filtering of Receive Packets
5.1.1.3.3Filter Broadcast Packets
5.1.1.3.6Filter CRC Error Packets
5.1.1.3.2Filter on Multicast Packet Match
5.1.1.3.4Filter VLAN Packets
5.1.1.4CRC Error Detection
5.1.2Flow Control
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5.1.2.1802.3x Flow Control Full-DuplexOperation
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5.1.2.1.1Pause Frame Format
SPI3 Interface
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5.1.2.1.2Pause Settings
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5.1.2.1.4Half-DuplexOperation
5.1.2.1.5Transmit Pause Control Interface
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“FC TX Timer Value $ Port_Index + 0x07 XOFF
“FC TX Timer Value $ Port_Index + 0x07 XOFF
“FC TX Timer Value $ Port_Index + 0x07 XOFF
“FC TX Timer Value $ Port_Index + 0x07 XOFF
5.1.3Mixed-ModeOperation
5.1.3.1Configuration of the IXF1104
5.1.3.2Key Configuration Registers
Datasheet
5.1.4Fiber Mode
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5.1.4.1Fiber Auto-Negotiation
5.1.5Copper Mode
5.1.4.3Fiber Forced Mode
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5.1.5.2Duplex
5.1.6Jumbo Packet Support
5.1.5.1Speed
5.1.5.3Copper Auto-Negotiation
5.1.6.3Loss-lessFlow Control
5.1.6.1Rx Statistics
5.1.6.2TX Statistics
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5.1.7.1TX and RX FIFO Operation 5.1.7.1.1TX FIFO
5.1.7Packet Buffer Dimensions
5.1.8RMON Statistics Support
5.1.7.1.2RX FIFO
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Table 25. RMON Additional Statistics Sheet 1 of
5.1.8.1Conventions
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5.2SPI3 Interface
5.1.8.2IXF1104 Advantages
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Data Path
5.2.1MPHY Operation
5.2.2MPHY Logical Timing
5.2.1.1SPI3 RX Round Robin Data Transmission
5.2.2.1Transmit Timing
5.2.2.2Receive Timing
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IXF1104 MPHY
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Network Processor
Line-SideInterface
5.2.2.4Parity
5.2.2.5SPHY Mode
5.2.2.3Clock Rates
5.2.2.5.1Data Path
5.2.2.8Receive Timing SPHY
5.2.2.6SPHY Logical Timing
5.2.2.7Transmit Timing SPHY
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Figure 15. SPHY Receive Logical Timing
5.2.2.8.1Clock Rates
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5.2.2.9.1RX SPI3 Flow Control
5.2.2.8.2Parity
5.2.2.9SPI3 Flow Control
5.2.2.9.2TX SPI3 Flow Control
PTPA
DTPA_0:3
STPA
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5.3Gigabit Media Independent Interface GMII
5.2.3Pre-PendingFunction
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5.3.1GMII Signal Multiplexing
5.3.2GMII Interface Signal Definition
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Transmit Error
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Transmit Enable
Receive Error
Intel IXF1104
Media Access Controller
5.4.1Multiplexing of Data and Control
Quad PHY Device
5.4.2Timing Specifics
5.4.3TX_ER and RX_ER Coding
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TD3:0_0:3
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TXC_0:3
TX_CTL_0:3
5.4.3.1In-BandStatus
5.5MDIO Control and Interface
5.4.410/100 Mbps Functionality
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5.5.2MDIO Register Descriptions
5.5.3Clear When Done
5.5.1MDIO Address
5.5.4MDC Generation
5.5.7MDI State Machine
5.5.6Single MDI Command Operation
5.5.5Management Frames
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Figure 22. MDI State
5.5.8Autoscan Operation
5.6.1Features
5.6SerDes Interface
5.6.2Functional Description
5.6.2.1Transmitter Operational Overview
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5.6.2.5Receiver Jitter Tolerance
5.6.2.4Selective Power-Down
5.6.2.3Receiver Operational Overview
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5.6.2.6Transmit Jitter
5.6.2.7Receive Jitter
Sinusoidal Jitter Mask
5.7Optical Module Interface
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5.7.2.1High-SpeedSerial Interface
5.7.2.2Low-SpeedStatus Signaling Interface
5.7.2Functional Descriptions
5.7.2.2.1MOD_DEF_0:3
5.7.2.2.6TX_FAULT_INT
5.7.2.2.2TX_FAULT_0:3
5.7.2.2.4TX_DISABLE_0:3
5.7.2.2.3RX_LOS_0:3
5.7.3.2I2C Read Operation
5.7.3I²C Module Configuration Interface
5.7.3.1I2C Control and Data Registers
•“I2C Control Ports 0 - 3 $0x79B” on page
5.7.3.3I2C Write Operation
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5.7.3.6Clock and Data Transitions
5.7.3.4I²C Protocol Specifics
5.7.3.5Port Protocol Operation
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5.7.3.6.3Acknowledge
5.7.3.6.1Start Condition
5.7.3.6.2Stop Condition
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5.7.3.6.6Random Read Operation
5.7.3.6.4Memory Reset
5.7.3.6.5Device Addressing
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5.8.1Modes of Operation
5.8.2LED Interface Signal Description
5.8LED Interface
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5.8.3Mode 0: Detailed Operation
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5.8.4Mode 1: Detailed Operation
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5.8.5Power-On,Reset, Initialization
5.8.6LED DATA Decodes
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5.8.6.1LED Signaling Behavior
5.8.6.1.1 Fiber LED Behavior
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5.9CPU Interface
5.8.6.1.2Copper LED Behavior
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5.9.1Functional Description
5.9.1.1Read Access
5.9.1.2Write Access
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5.9.2Endian
5.9.1.3CPU Timing Parameters
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5.10TAP Interface JTAG
5.10.1TAP State Machine
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Table 38. Instruction Register Description
5.10.4Boundary Scan Register
5.11Loopback Modes
5.10.3ID Register
5.10.5Bypass Register
5.11.2Line Side Interface Loopback
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5.12Clocks
5.12.1System Interface Reference Clocks
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5.12.4MDC Clock
5.12.2SPI3 Receive and Transmit Clocks
5.12.3RGMII Clocks
5.12.1.1CLK125
5.12.7LED Clock
5.12.5JTAG Clock
5.12.6I2C Clock
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6.1Change Port Mode Initialization Sequence
6.0Applications
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13.Assert set to 1 “Port Enable $0x500”
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7.0Electrical Specifications
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7.1DC Specifications
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Table 41. Intel IXF1104 MAC DC Specifications
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7.1.1Undershoot / Overshoot Specifications
7.1.2RGMII Electrical Characteristics
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Table 45. RGMII Power
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7.2SPI3 AC Timing Specifications
7.2.1Receive Interface Timing
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7.2.2Transmit Interface Timing
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7.3RGMII AC Timing Specification
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7.4.1.11000 BASE-TTransmit Interface
7.4GMII AC Timing Specification
7.4.11000 Base-TOperation
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7.4.1.21000BASE-TReceive Interface
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7.5SerDes AC Timing Specification
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7.6.2MDC Low-SpeedOperation Timing
7.6MDIO AC Timing Specification
7.6.1MDC High-SpeedOperation Timing
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MDIO
7.6.3MDIO AC Timing
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MDC MDIO
7.7Optical Module and I2C AC Timing Specification
7.7.1I2C Interface Timing
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7.8.2CPU Interface Write Cycle AC Timing
7.8CPU AC Timing Specification
7.8.1CPU Interface Read Cycle AC Timing
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7.9Transmit Pause Control AC Timing Specification
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7.10JTAG AC Timing Specification
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7.11System AC Timing Specification
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7.12LED AC Timing Specification
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8.2Graphical Representation
8.0Register Set
8.1Document Structure
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8.3Per Port Registers
8.4Register Map
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Table 68. SerDes Registers $ 0x780 -
Source MAC address bit
8.4.1MAC Control Registers
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Source MAC address bit
Table 73. Collision Distance $ Port_Index +
Table 75. FC TX Timer Value $ Port_Index +
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Table 74. Collision Threshold $ Port_Index +
Table 78. IPG Receive Time 2 $ Port_Index + 0x0B
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Table 77. IPG Receive Time 1 $ Port_Index + 0x0A
Table 79. IPG Transmit Time $ Port_Index + 0x0C
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Table 80. Pause Threshold $ Port_Index + 0x0E
Table 81. Max Frame Size Addr: Port_Index + 0x0F
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Table 83. Flush TX $ Port_Index +
Table 84. FC Enable $ Port_Index +
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Table 85. FC Back Pressure Length $ Port_Index +
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8.4.2MAC RX Statistics Register Overview
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8.4.3MAC TX Statistics Register Overview
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8.4.4PHY Autoscan Registers
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Table 103. Port Enable $0x500
Table 104. Interface Mode $0x501
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Table 105. Link LED Enable $0x502
Table 106. MAC Soft Reset $0x505
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Table 108. CPU Interface $0x508
Table 107. MDIO Soft Reset $0x506
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Table 109. LED Control $0x509
Table 111. LED Fault Disable $0x50B
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Table 110. LED Flash Rate $0x50A
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Table 112. JTAG ID $0x50C
8.4.6RX FIFO Register Overview
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Table 117. RX FIFO Low Watermark Port 0 $0x58A
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Table 116. RX FIFO High Watermark Port 3 $0x583
Table 118. RX FIFO Low Watermark Port 1 $0x58B
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Table 119. RX FIFO Low Watermark Port 2 $0x58C
Table 120. RX FIFO Low Watermark Port 3 $0x58D
Table 122. RX FIFO Port Reset $0x59E
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Table 124. RX FIFO Overflow Event $0x5A0
Packet Filter Control $ Port_Index +
with the“RX FIFO Errored Frame
Drop Enable $0x59F” and the “RX
0x19”
with the“RX FIFO Errored Frame
with the“RX FIFO Errored Frame
Drop Enable $0x59F” and the “RX
Drop Enable $0x59F” and the “RX
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High watermark for TX FIFO Port 0. The
8.4.7TX FIFO Register Overview
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High watermark for TX FIFO Port 1. The
Low watermark for TX FIFO Port 1. The
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Low watermark for TX FIFO Port 0. The
Low watermark for TX FIFO Port 2. The
MAC threshold for TX FIFO Port 1. The
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MAC threshold for TX FIFO Port 0. The
MAC threshold for TX FIFO Port 2. The
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Register Description: TX FIFO Underflow Event
Register Description: TX FIFO Overflow Event
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Table 137. TX FIFO Port Reset $0x620 Sheet 2 of
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Table 141. TX FIFO Port Drop Enable $0x63D
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8.4.8MDIO Register Overview
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Table 144. Autoscan PHY Address Enable $0x682
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Table 145. MDIO Control $0x683
SPHY/MPHY Mode
8.4.9SPI3 Register Overview
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SPHY/MPHY Mode
SPHY Mode
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SPHY/MPHY Mode
MPHY Mode
MPHY Mode
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SPHY Mode
SPHY Mode
MPHY Mode
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SPHY Mode
SPHY Mode
MPHY Mode
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SPHY Mode
SPHY Mode
MPHY Mode
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SPHY Mode
SPHY Mode
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8.4.10SerDes Register Overview
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8.4.11Optical Module Register Overview
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Table 155. I2C Control Ports 0 - 3 $0x79B
Table 156. I2C Data Ports 0 - 3 $0x79F
9.1Overview
9.0Mechanical Specifications
9.1.1Features
9.2Package Specifics for the IXF1104
= Ball
9.3Package Information
Datasheet
= No ball
Figure 56. CBGA Package Side View Diagram
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Syww9001
9.3.1Example Package Marking
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Pin 1 mark Syww9001 Country
10.0Product Ordering Information
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Tray