IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller

5.1.1.3.2Filter on Multicast Packet Match

This feature is enabled when bit 1 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1. Any frame received in this mode that does not match the Port Multicast Address (reserved multicast address recognized by MAC) is marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0 in “SPI3 Receive Configuration ($0x701)” on page 214).

When bit 1 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0, all multicast frames are sent out the SPI3 interface.

5.1.1.3.3Filter Broadcast Packets

This feature is enabled when bit 2 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1. Any broadcast frame received in this mode is marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1.

Otherwise, the frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0 in “SPI3 Receive Configuration ($0x701)” on page 214).

When bit 2 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0, all broadcast frames are sent out the SPI3 interface.

5.1.1.3.4Filter VLAN Packets

This feature is enabled when bit 3 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1. VLAN frames received in this mode are marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the VLAN frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0 in “SPI3 Receive Configuration ($0x701)” on page 214).

When bit 3 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0, all VLAN frames are sent out the SPI3 interface.

5.1.1.3.5Filter Pause Packets

This feature is enabled when bit 4 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0. Pause frames received in this mode are marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the pause frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0 in “SPI3 Receive Configuration ($0x701)” on page 214).

When bit 4 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1, all pause frames are sent out the SPI3 interface.

Note: Pause packets are not filtered if flow control is disabled in the “FC Enable ($ Port_Index + 0x12)”.

5.1.1.3.6Filter CRC Error Packets

This feature is enabled when bit 5 of the “RX Packet Filter Control ($ Port_Index + 0x19)” = 0. Frames received with an errored CRC are marked as bad frames and may optionally be dropped in the RX FIFO. Otherwise, the frames are sent to the SPI3 interface and may be optionally signaled with an RERR (see Table 22 “CRC Errored Packets Drop Enable Behavior” on page 68).

Datasheet

67

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

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Image 67
Intel IXF1104 manual Filter on Multicast Packet Match, Filter Broadcast Packets, Filter Vlan Packets, Filter Pause Packets

IXF1104 specifications

The Intel IXF1104 is a cutting-edge Network Interface Controller (NIC) designed to meet the needs of high-speed communication in modern networking environments. As the demand for bandwidth-intensive applications continues to grow, Intel's IXF1104 is engineered to deliver exceptional performance, reliability, and scalability, making it an ideal choice for data centers and enterprise networks.

One of the main features of the IXF1104 is its support for high-speed Ethernet connectivity, providing up to 100 Gbps throughput. This capability allows organizations to handle large amounts of data traffic efficiently, accommodating everything from cloud computing to big data analytics. The NIC utilizes advanced packet processing technology which ensures minimal latency, enhancing the overall user experience.

The IXF1104 is built on a robust architecture that integrates Intel's latest processing technologies. It incorporates a multi-core processing engine that allows for parallel processing of network packets, improving the handling of simultaneous network requests. This architecture also supports offloading features, freeing up CPU resources for other critical tasks, which optimizes system performance.

In terms of technologies, the IXF1104 supports a variety of standards including Ethernet and Fiber Channel, making it versatile across different networking environments. Its compatibility with industry-standard networking protocols ensures that it can easily integrate into existing frameworks, facilitating seamless upgrades and expansions.

Another significant characteristic of the IXF1104 is its energy efficiency. With Intel’s focus on sustainability, this NIC is designed to consume less power relative to its performance output, thereby reducing overall operational costs for organizations. It employs dynamic power management features that adjust power usage based on demand, which is especially beneficial in large-scale deployments.

Additionally, security features are woven into the IXF1104 design, protecting sensitive data from potential threats. Hardware-based security functions, including encryption capabilities and secure boot processes, ensure that the NIC can safeguard data integrity against unauthorized access.

Overall, the Intel IXF1104 stands out in the crowded NIC market by offering high-performance capabilities, energy efficiency, and robust security features. Its combination of advanced technologies and characteristics positions it as a strategic asset for modern networks, empowering organizations to achieve their connectivity and performance goals in an increasingly data-driven world.