Intel IXF1104 manual 7.3RGMII AC Timing Specification, Datasheet

IXF1104 4-Port Gigabit Ethernet Media Access Controller

7.3RGMII AC Timing Specification

Figure 37 and Table 48 provide RGMII interface timing parameters.

Figure 37. RGMII Interface Timing

TXC
(at Transmitter)
		TSkewT
TD[3:0]	TD[3:0]	TD[7:4]
TX_CTL[n]	TXEN	TXERR

TXC

(at Receiver)

RXC

(at Transmitter)

TSkewT

RD[3:0]	RD[3:0]	RD[7:4]
RX_CTL	RXDV	RXERR

RXC

(at Receiver)

TSkewR

TSkewR

B3251-01

Table 48. RGMII Interface Timing Parameters

Symbol		Parameter	Min	Typ	Max	Unit
TskewT		Data-to-Clock Output Skew (at Transmitter)	-500	0	500	ps
TskewR		Data-to-Clock Input Skew (at Receiver)1	1	–	2.8	ns
Tcyc		Clock Cycle Duration2	7.2	8	8.8	ns
Duty_T		Duty Cycle for Gigabit2	45	50	55	%
Duty_G		Duty Cycle for 10/100T3	40	50	60	%
Tr/Tf		Rise/Fall Time (20–80%)	–	–	.75	ns
1.	This implies that PC board design requires clocks to be routed so that an additional trace delay of greater
	than 1.5 ns is added to the associated clock signal.
2.	For 10 Mbps and 100 Mbps Tcyc scales to 400 ns +/– 40 ns and 40 ns +/– 4 ns respectively.
3.	Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet’s
	clock domain, as long as minimum duty cycle is not violated and stretching occurs for no more than three
	Tcyc of the lowest speed transitioned between.

140 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004