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Intel IXF1104 manual 5.12Clocks, 5.12.1System Interface Reference Clocks, Datasheet

Models: IXF1104

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5.12Clocks

IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller

Figure 34. Line Side Interface Loopback Path

	Line Side	Internal Loopback
TX	TX FIFO
SPI3 Interface		MAC	Line Side
Block		MAC	Interface
Block			Interface
	RX FIFO
RX
			B3230-01

When the IXF1104 is configured in this loopback mode, all of the MAC functions and features are available, including flow control and pause-packet generation.

To configure the IXF1104 to use the line-side loopback mode, the “Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)" must be configured. Each IXF1104 port has a unique bit in this register designated to control the loopback. It is possible to have individual ports in a loopback mode while other ports continue to operate in a normal mode.

Note: Line side interface loopback packets also appear at the SPI3 interface.

5.12Clocks

The IXF1104 system interface has several reference clocks, including the following:

•SPI3 data path input clocks

•RGMII input and output clocks

•MDIO output clock

•JTAG input clock

•I2C clock

•LED output clock.

This section details the unique clock source requirements.

5.12.1System Interface Reference Clocks

The following system interface clock is required by the IXF1104:

•CLK125

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Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Image 126

Intel IXF1104 manual 5.12Clocks, 5.12.1System Interface Reference Clocks, Datasheet

Contents

Product Features DatasheetDatasheet ApplicationsContents ContentsIntroduction DatasheetContents DatasheetContents DatasheetApplications ContentsDatasheet Contents Figures10.0 DatasheetTables ContentsDatasheet Contents DatasheetContents DatasheetContents DatasheetRevision History ContentsDatasheet Revision Number: ContentsDatasheet Revision Date: March 25,Contents DatasheetRevision Number: Revision Date: March 25, ContentsDatasheet Sheet 4 of Page # DescriptionRevision Number: Revision Date: March 25, ContentsDatasheet Sheet 5 ofContents DatasheetContents Datasheet1.2Related Documents 1.0Introduction1.1What You Will Find in This Document Datasheet2.0General Description DatasheetDatasheet Figure 2. Internal ArchitectureDatasheet 3.0Ball Assignments and Ball List Tables3.1Ball Assignments = No Pad A12.SPI3 Ball Connection 3.2Ball List Tables1.GMII Ball Connection 3.Fiber Mode Ball ConnectionDatasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Document Number: Revision Number:Revision Date: March 25, 4.1.1Signal Name Conventions 4.0Ball Assignments and Signal Descriptions4.1Naming Conventions DatasheetSPHY MPHY 4.2Interface Signal GroupsDatasheet GMIIMode 4.3Signal Description TablesDatasheet BitsTransmit Error DatasheetTransmit Write Enable Transmit Parity32-bit Multi-PHYmode: TMOD1:0 DatasheetTMOD1:0 Transmit Word Modulo 4 x 8 Single-PHYmode: MOD1:0 is notDatasheet DTPA_0:3 Direct Transmit PacketAvailable Receive Data Bus DatasheetPolled-PHYTransmit Packet Available ModeReceive Data Bus DatasheetReceive Read Enable Mode32-bit Multi-PHYmode: RERR_0 covers DatasheetReceive Error 4 x 8 Single-PHYmode: The RERR_0:332-bit Multi-PHYmode: REOP_0 covers DatasheetReceive End of Packet 4 x 8 Single-PHYmode: The REOP_0:3Table 4. SerDes Interface Signal Descriptions DatasheetTransmit Error DatasheetTransmit Enable Transmit DataReceive Data DatasheetReceive Error Receive Data ValidTransmit Data DatasheetSource Synchronous Transmit Clock Transmit ControlDatasheet Receive DataReceive Control Data bus DatasheetCycle complete indicator 32-bitmode: Uses 31:0Datasheet Transmit DisableReceiver Loss of Signal Interrupt Transmitter Fault Interrupt Table 10. MDIO Interface Signal DescriptionsDatasheet Module Definition InterruptTable 13. System Interface Signal Descriptions Table 11. LED Interface Signal DescriptionsTable 12. JTAG Interface Signal Descriptions DatasheetTable 14. Power Supply Signal Descriptions Datasheet4.4Ball Usage Summary DatasheetTotal 4.5Multiplexed Ball Connections Datasheet4.5.2SPI3 MPHY/SPHY Ball Connections DatasheetDatasheet Table 17. SPI3 MPHY/SPHY Interface Sheet 2 of4.6Ball State During Reset DatasheetDatasheet 4.7.2Power-DownSequence 4.7Power Supply Sequencing4.7.1Power-UpSequence Datasheet4.9Analog Power Filtering 4.8Pull-Up/Pull-DownBall GuidelinesDatasheet 2.5 or 1.8 Power BallDatasheet Analog5.1Media Access Controller MAC 5.0Functional DescriptionsDatasheet 5.1.1.2Automatic CRC Generation 5.1.1Features for Fiber and Copper Mode5.1.1.1Padding of Undersized Frames on Transmit 5.1.1.3Filtering of Receive Packets5.1.1.3.3Filter Broadcast Packets 5.1.1.3.6Filter CRC Error Packets5.1.1.3.2Filter on Multicast Packet Match 5.1.1.3.4Filter VLAN Packets5.1.1.4CRC Error Detection 5.1.2Flow ControlDatasheet 5.1.2.1802.3x Flow Control Full-DuplexOperation Datasheet5.1.2.1.1Pause Frame Format SPI3 InterfaceDatasheet 5.1.2.1.2Pause Settings Datasheet5.1.2.1.4Half-DuplexOperation 5.1.2.1.5Transmit Pause Control InterfaceDatasheet “FC TX Timer Value $ Port_Index + 0x07 XOFF “FC TX Timer Value $ Port_Index + 0x07 XOFF“FC TX Timer Value $ Port_Index + 0x07 XOFF “FC TX Timer Value $ Port_Index + 0x07 XOFF5.1.3Mixed-ModeOperation 5.1.3.1Configuration of the IXF11045.1.3.2Key Configuration Registers Datasheet5.1.4Fiber Mode Datasheet5.1.4.3Fiber Forced Mode 5.1.5Copper Mode5.1.4.1Fiber Auto-Negotiation Datasheet5.1.5.2Duplex 5.1.6Jumbo Packet Support5.1.5.1Speed 5.1.5.3Copper Auto-Negotiation5.1.6.3Loss-lessFlow Control 5.1.6.1Rx Statistics5.1.6.2TX Statistics Datasheet5.1.7.1TX and RX FIFO Operation 5.1.7.1.1TX FIFO 5.1.7Packet Buffer Dimensions5.1.8RMON Statistics Support 5.1.7.1.2RX FIFODatasheet Table 25. RMON Additional Statistics Sheet 1 of5.1.8.1Conventions Datasheet5.2SPI3 Interface 5.1.8.2IXF1104 AdvantagesDatasheet Data Path 5.2.1MPHY Operation5.2.2MPHY Logical Timing 5.2.1.1SPI3 RX Round Robin Data Transmission5.2.2.1Transmit Timing 5.2.2.2Receive TimingDatasheet IXF1104 MPHY DatasheetNetwork Processor Line-SideInterface5.2.2.5SPHY Mode 5.2.2.3Clock Rates5.2.2.4Parity 5.2.2.5.1Data Path5.2.2.8Receive Timing SPHY 5.2.2.6SPHY Logical Timing5.2.2.7Transmit Timing SPHY DatasheetDatasheet Figure 15. SPHY Receive Logical Timing5.2.2.8.1Clock Rates Datasheet5.2.2.9.1RX SPI3 Flow Control 5.2.2.8.2Parity5.2.2.9SPI3 Flow Control 5.2.2.9.2TX SPI3 Flow ControlPTPA DTPA_0:3STPA Datasheet5.3Gigabit Media Independent Interface GMII 5.2.3Pre-PendingFunctionDatasheet 5.3.1GMII Signal Multiplexing 5.3.2GMII Interface Signal DefinitionDatasheet Transmit Error DatasheetTransmit Enable Receive ErrorIntel IXF1104 Media Access Controller5.4.1Multiplexing of Data and Control Quad PHY Device5.4.2Timing Specifics 5.4.3TX_ER and RX_ER CodingDatasheet TD3:0_0:3 DatasheetTXC_0:3 TX_CTL_0:35.4.3.1In-BandStatus 5.5MDIO Control and Interface5.4.410/100 Mbps Functionality Datasheet5.5.2MDIO Register Descriptions 5.5.3Clear When Done5.5.1MDIO Address 5.5.4MDC Generation5.5.7MDI State Machine 5.5.6Single MDI Command Operation5.5.5Management Frames DatasheetDatasheet Figure 22. MDI State5.5.8Autoscan Operation 5.6.1Features5.6SerDes Interface 5.6.2Functional Description5.6.2.1Transmitter Operational Overview Datasheet5.6.2.5Receiver Jitter Tolerance 5.6.2.4Selective Power-Down5.6.2.3Receiver Operational Overview DatasheetDatasheet 5.6.2.6Transmit Jitter5.6.2.7Receive Jitter Sinusoidal Jitter Mask5.7Optical Module Interface Datasheet5.7.2.1High-SpeedSerial Interface 5.7.2.2Low-SpeedStatus Signaling Interface5.7.2Functional Descriptions 5.7.2.2.1MOD_DEF_0:35.7.2.2.6TX_FAULT_INT 5.7.2.2.2TX_FAULT_0:35.7.2.2.4TX_DISABLE_0:3 5.7.2.2.3RX_LOS_0:35.7.3.2I2C Read Operation 5.7.3I²C Module Configuration Interface5.7.3.1I2C Control and Data Registers •“I2C Control Ports 0 - 3 $0x79B” on page5.7.3.3I2C Write Operation Datasheet5.7.3.6Clock and Data Transitions 5.7.3.4I²C Protocol Specifics5.7.3.5Port Protocol Operation Datasheet5.7.3.6.3Acknowledge 5.7.3.6.1Start Condition5.7.3.6.2Stop Condition Datasheet5.7.3.6.6Random Read Operation 5.7.3.6.4Memory Reset5.7.3.6.5Device Addressing Datasheet5.8.1Modes of Operation 5.8.2LED Interface Signal Description5.8LED Interface Datasheet5.8.3Mode 0: Detailed Operation Datasheet5.8.4Mode 1: Detailed Operation Datasheet5.8.5Power-On,Reset, Initialization 5.8.6LED DATA DecodesDatasheet 5.8.6.1LED Signaling Behavior 5.8.6.1.1 Fiber LED BehaviorDatasheet 5.9CPU Interface 5.8.6.1.2Copper LED BehaviorDatasheet 5.9.1Functional Description 5.9.1.1Read Access5.9.1.2Write Access Datasheet5.9.2Endian 5.9.1.3CPU Timing ParametersDatasheet 5.10TAP Interface JTAG 5.10.1TAP State MachineDatasheet Datasheet Table 38. Instruction Register Description5.10.4Boundary Scan Register 5.11Loopback Modes5.10.3ID Register 5.10.5Bypass Register5.11.2Line Side Interface Loopback Datasheet5.12Clocks 5.12.1System Interface Reference ClocksDatasheet 5.12.4MDC Clock 5.12.2SPI3 Receive and Transmit Clocks5.12.3RGMII Clocks 5.12.1.1CLK1255.12.7LED Clock 5.12.5JTAG Clock5.12.6I2C Clock Datasheet6.0Applications 6.1Change Port Mode Initialization SequenceDatasheet 13.Assert set to 1 “Port Enable $0x500” Datasheet7.0Electrical Specifications Datasheet7.1DC Specifications DatasheetTable 41. Intel IXF1104 MAC DC Specifications Datasheet7.1.1Undershoot / Overshoot Specifications 7.1.2RGMII Electrical CharacteristicsDatasheet Table 45. RGMII Power Datasheet7.2SPI3 AC Timing Specifications 7.2.1Receive Interface TimingDatasheet Datasheet 7.2.2Transmit Interface Timing DatasheetDatasheet 7.3RGMII AC Timing Specification Datasheet7.4.1.11000 BASE-TTransmit Interface 7.4GMII AC Timing Specification7.4.11000 Base-TOperation Datasheet7.4.1.21000BASE-TReceive Interface Datasheet7.5SerDes AC Timing Specification Datasheet7.6.2MDC Low-SpeedOperation Timing 7.6MDIO AC Timing Specification7.6.1MDC High-SpeedOperation Timing DatasheetMDIO 7.6.3MDIO AC TimingDatasheet MDC MDIO7.7Optical Module and I2C AC Timing Specification 7.7.1I2C Interface TimingDatasheet Datasheet 7.8.2CPU Interface Write Cycle AC Timing 7.8CPU AC Timing Specification7.8.1CPU Interface Read Cycle AC Timing DatasheetDatasheet 7.9Transmit Pause Control AC Timing Specification Datasheet7.10JTAG AC Timing Specification Datasheet7.11System AC Timing Specification Datasheet7.12LED AC Timing Specification Datasheet8.2Graphical Representation 8.0Register Set8.1Document Structure Datasheet8.3Per Port Registers 8.4Register MapDatasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Table 68. SerDes Registers $ 0x780 -Source MAC address bit 8.4.1MAC Control RegistersDatasheet Source MAC address bitTable 73. Collision Distance $ Port_Index + Table 75. FC TX Timer Value $ Port Index +Datasheet Table 74. Collision Threshold $ Port_Index +Table 78. IPG Receive Time 2 $ Port_Index + 0x0B DatasheetTable 77. IPG Receive Time 1 $ Port_Index + 0x0A Table 79. IPG Transmit Time $ Port_Index + 0x0CDatasheet Table 80. Pause Threshold $ Port_Index + 0x0ETable 81. Max Frame Size Addr: Port_Index + 0x0F Datasheet Table 83. Flush TX $ Port_Index +Table 84. FC Enable $ Port_Index + DatasheetTable 85. FC Back Pressure Length $ Port_Index + Datasheet Datasheet Datasheet Datasheet Datasheet 8.4.2MAC RX Statistics Register Overview DatasheetDatasheet Datasheet Datasheet 8.4.3MAC TX Statistics Register Overview DatasheetDatasheet Datasheet 8.4.4PHY Autoscan Registers DatasheetDatasheet Datasheet Datasheet Datasheet Datasheet Datasheet Table 103. Port Enable $0x500 DatasheetTable 104. Interface Mode $0x501 Table 105. Link LED Enable $0x502 Table 106. MAC Soft Reset $0x505Datasheet Table 108. CPU Interface $0x508 Table 107. MDIO Soft Reset $0x506Datasheet Table 109. LED Control $0x509Table 111. LED Fault Disable $0x50B DatasheetTable 110. LED Flash Rate $0x50A Datasheet Table 112. JTAG ID $0x50C8.4.6RX FIFO Register Overview DatasheetTable 117. RX FIFO Low Watermark Port 0 $0x58A DatasheetTable 116. RX FIFO High Watermark Port 3 $0x583 Table 118. RX FIFO Low Watermark Port 1 $0x58BDatasheet Table 119. RX FIFO Low Watermark Port 2 $0x58CTable 120. RX FIFO Low Watermark Port 3 $0x58D Table 122. RX FIFO Port Reset $0x59E DatasheetDatasheet Table 124. RX FIFO Overflow Event $0x5A0Packet Filter Control $ Port_Index + with the“RX FIFO Errored FrameDrop Enable $0x59F” and the “RX 0x19”with the“RX FIFO Errored Frame with the“RX FIFO Errored FrameDrop Enable $0x59F” and the “RX Drop Enable $0x59F” and the “RXDatasheet Datasheet Datasheet High watermark for TX FIFO Port 0. The 8.4.7TX FIFO Register OverviewDatasheet High watermark for TX FIFO Port 1. TheLow watermark for TX FIFO Port 1. The DatasheetLow watermark for TX FIFO Port 0. The Low watermark for TX FIFO Port 2. TheMAC threshold for TX FIFO Port 1. The DatasheetMAC threshold for TX FIFO Port 0. The MAC threshold for TX FIFO Port 2. TheDatasheet Register Description: TX FIFO Underflow EventRegister Description: TX FIFO Overflow Event Datasheet Table 137. TX FIFO Port Reset $0x620 Sheet 2 of DatasheetDatasheet Table 141. TX FIFO Port Drop Enable $0x63D Datasheet8.4.8MDIO Register Overview DatasheetTable 144. Autoscan PHY Address Enable $0x682 DatasheetTable 145. MDIO Control $0x683 SPHY/MPHY Mode 8.4.9SPI3 Register OverviewDatasheet SPHY/MPHY ModeSPHY Mode DatasheetSPHY/MPHY Mode MPHY ModeMPHY Mode DatasheetSPHY Mode SPHY ModeMPHY Mode DatasheetSPHY Mode SPHY ModeMPHY Mode DatasheetSPHY Mode SPHY ModeMPHY Mode DatasheetSPHY Mode SPHY ModeDatasheet 8.4.10SerDes Register Overview DatasheetDatasheet 8.4.11Optical Module Register Overview DatasheetDatasheet Table 155. I2C Control Ports 0 - 3 $0x79BTable 156. I2C Data Ports 0 - 3 $0x79F 9.1Overview 9.0Mechanical Specifications9.1.1Features 9.2Package Specifics for the IXF1104= Ball 9.3Package InformationDatasheet = No ballFigure 56. CBGA Package Side View Diagram DatasheetSyww9001 9.3.1Example Package MarkingDatasheet Pin 1 mark Syww9001 Country10.0Product Ordering Information DatasheetTray