Intel IXF1104 manual Datasheet

Models: IXF1104

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IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 152. Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)

Bit

Name

Description

 

Type1

Default

 

 

 

 

 

Register Description: This register is used when a change to the operational mode or speed

 

of the IXF1104 is required. This register ensures that when a change is made that the internal

0x00000000

clocking of the IXF1104 is managed correctly and no unexpected effects of the operational or

 

speed change are observable on the line interfaces.

 

 

 

 

 

 

 

 

 

31:4

Reserved

Reserved

 

RO

0x0000000

 

 

 

 

 

 

 

Enables internal clock generator for Port 3 to

 

 

 

 

sample the “MAC IF Mode and RGMII Speed ($

 

 

 

 

Port_Index + 0x10)" and the

“Interface Mode

 

 

 

Clock and Interface

($0x501)".

 

 

 

 

0 = Set to zero when changes are being made to

R/W

0

3

Mode Change Enable

 

Port 32

the “MAC IF Mode and RGMII Speed ($

 

 

 

 

Port_Index + 0x10)" and the “Interface Mode

 

 

 

 

($0x501)".

 

 

 

 

 

1 = Set to 1 for the configuration changes to take

 

 

 

 

effect.

 

 

 

 

 

 

 

 

 

 

Enables internal clock generator for Port 2 to

 

 

 

 

sample the “MAC IF Mode and RGMII Speed ($

 

 

 

 

Port_Index + 0x10)" and the

“Interface Mode

 

 

 

Clock and Interface

($0x501)".

 

 

 

 

0 = Set to zero when changes are being made to

 

 

2

Mode Change Enable

R/W

0

the “MAC IF Mode and RGMII Speed ($

 

Port 22

 

 

 

 

Port_Index + 0x10)" and the “Interface Mode

 

 

 

 

($0x501)".

 

 

 

 

 

1 = Set to 1 for the configuration changes to take

 

 

 

 

effect.

 

 

 

 

 

 

 

 

 

 

Enables internal clock generator for Port 1 to

 

 

 

 

sample the “MAC IF Mode and RGMII Speed ($

 

 

 

 

Port_Index + 0x10)" and the

“Interface Mode

 

 

 

Clock and Interface

($0x501)".

 

 

 

 

0 = Set to zero when changes are being made to

 

 

1

Mode Change Enable

R/W

0

 

Port 12

the “MAC IF Mode and RGMII Speed ($

 

 

 

 

Port_Index + 0x10)" and the “Interface Mode

 

 

 

 

($0x501)".

 

 

 

 

 

1 = Set to 1 for the configuration changes to take

 

 

 

 

effect.

 

 

 

 

 

 

 

 

 

 

Enables internal clock generator for Port 0 to

 

 

 

 

sample the “MAC IF Mode and RGMII Speed ($

 

 

 

 

Port_Index + 0x10)" and the

“Interface Mode

 

 

 

Clock and Interface

($0x501)".

 

 

 

 

0 = Set to zero when changes are being made to

 

 

0

Mode Change Enable

R/W

0

the “MAC IF Mode and RGMII Speed ($

 

Port 02

 

 

 

 

Port_Index + 0x10)" and the “Interface Mode

 

 

 

 

($0x501)".

 

 

 

 

 

1 = Set to 1 for the configuration changes to take

 

 

 

 

effect.

 

 

 

 

 

 

 

 

 

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

2. Refer to Section 6.1, “Change Port Mode Initialization Sequence” on page 129 for the proper sequence to change the port mode and speed in conjunction with this register.

220

Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Page 220
Image 220
Intel IXF1104 manual Datasheet