Intel IXF1104 manual Datasheet

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 148. Address Parity Error Packet Drop Counter ($0x70A)

Bit	Name	Description	Type1	Default
Register Description: This register counts the number of packets dropped due to parity error				0x00000000
detection during the address selection cycle.
31:8	Reserved	Reserved	RO	0x000000
		This is an 8-bit counter that counts the number of
		packets dropped due to parity error detection
		during the address selection cycle. This gets
7:0	Address Parity Error	cleared when read and saturates at 8’hFF. There	R	0x00
	Packet Drop Counter	is only one counter for address parity drop as
		address will be used only in MPHY mode of
		operation. The counter gets cleared once the
		register is read.

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

218 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004