IXF1104
Table 127. RX FIFO Padding and CRC Strip Enable ($0x5B3)
Bit | Name | Description | Type1 | Default | ||
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Register Description: This control register enables to | 0x00000000 | |||||
bytes and also enables the CRC stripping of a packet. |
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31:8 | Reserved | Reserved | RO | 0x000000 | ||
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| CRC Stripping Enable | CRC stripping is enabled for Port 3. |
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7 | 0 = | Disabled | R/W | 0 | ||
for Port 3 | ||||||
| 1 = | Enabled |
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| CRC Stripping Enable | CRC stripping is enabled for Port 2. |
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6 | 0 = | Disabled | R/W | 0 | ||
for Port 2 | ||||||
| 1 = | Enabled |
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| CRC Stripping Enable | CRC stripping is enabled for Port 1. |
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5 | 0 = | Disabled | R/W | 0 | ||
for Port 1 | ||||||
| 1 = | Enabled |
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| CRC Stripping Enable | CRC stripping is enabled for Port 0. |
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4 | 0 = | R/W | 0 | |||
for Port 0 | ||||||
| 1 = |
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| Enables |
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3 | every packet – Port 3. | R/W | 0 | |||
Port 3 | 0 = | Disabled | ||||
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| 1 = | Enabled |
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| Enables |
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2 | every packet – Port 2. | R/W | 0 | |||
Port 2 | 0 = | Disabled | ||||
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| 1 = | Enabled |
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| Enables |
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1 | every packet – Port 1. | R/W | 0 | |||
Port 1 | 0 = | Disabled | ||||
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| 1 = | Enabled |
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| Enables |
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0 | every packet – Port 0. | R/W | 0 | |||
Port 0 | 0 = | Disabled | ||||
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| 1 = | Enabled |
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1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
2.
Datasheet | 199 |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004