Intel IXF1104 manual Datasheet, SPHY Mode, MPHY Mode

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 146. SPI3 Transmit and Global Configuration ($0x700) (Sheet 3 of 3)

Bit	Name	Description	Type1	Default
		SPHY Mode:
		0 = Disables the selected SPI3 TX port 2
2	Tx_port_enable Port 2	1 = Enables the selected SPI3 TX port 2	R/W	0
		MPHY Mode:
		0 = Disables the selected SPI3 TX port 2
		1 = Enables the selected SPI3 TX port 2
		SPHY Mode:
		0 = Disables the selected SPI3 TX port 1
1	Tx_port_enable Port 1	1 = Enables the selected SPI3 TX port 1	R/W	0
		MPHY Mode:
		0 = Disables the selected SPI3 TX port 1
		1 = Enables the selected SPI3 TX port 1
		SPHY Mode:
		0 = Disables the selected SPI3 TX port 0
0	Tx_port_enable Port 0	1 = Enables the selected SPI3 TX port 0	R/W	0
		MPHY Mode:
		0 = Disables the selected SPI3 TX port 0
		1 = Enables the selected SPI3 TX port 0

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Table 147. SPI3 Receive Configuration ($0x701)

Bit	Name	Description	Type1	Default
Register Description: This register gives the configuration related to the SPI3 receiver.				0x00000F80
31:28	Reserved	Reserved	RO	0x0
		SPHY Mode:
		Indicates the number of pause cycles to be
		introduced between back-to-back transfers for
27	B2B_PAUSE Port 3	port 3.	R/W	0
		0 = Zero pause cycles
		1 = Two pause cycles
		MPHY Mode:
		NA
		SPHY Mode:
		Indicates the number of pause cycles to be
		introduced between back-to-back transfers for
26	B2B_PAUSE Port 2	port 2.	R/W	0
		0 = Zero pause cycles
		1 = Two pause cycles
		MPHY Mode:
		NA

1.RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

214 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004