Intel IXF1104 manual TX FIFO Port Reset $0x620 Sheet 2 of, Datasheet

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 137. TX FIFO Port Reset ($0x620) (Sheet 2 of 2)

Bit	Name	Description		Type1	Default
		Port 2
2	Port 2 Reset	0 =	De-assert Reset	R/W	0
		1 =	Assert Reset
		Port 1
1	Port 1 Reset	0 =	De-assert Reset	R/W	0
		1 =	Assert Reset
		Port 0
0	Port 0 Reset	0 =	De-assert Reset	R/W	0
		1 =	Assert Reset

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Table 138. TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)

Name	Description	Address	Type*	Default
TX FIFO overflow	When TX FIFO on Port 0 becomes full or
	reset, the number of frames lost or removed	0x621	R	0x00000000
frame drop counter
	on this port is shown in this register. This
on Port 0
	register is cleared on Read.
TX FIFO overflow	When TX FIFO on Port 1 becomes full or
	reset, the number of frames lost or removed	0x622	R	0x00000000
frame drop counter
	on this port is shown in this register. This
on Port 1
	register is cleared on Read.
TX FIFO overflow	When TX FIFO on Port 2 becomes full or
	reset, the number of frames lost or removed	0x623	R	0x00000000
frame drop counter
	on this port is shown in this register. This
on Port 2
	register is cleared on Read.
TX FIFO overflow	When TX FIFO on Port 3 becomes full or
	reset, the number of frames lost or removed	0x624	R	0x00000000
frame drop counter
	on this port is shown in this register. This
on Port 3
	register is cleared on Read.

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Datasheet 207

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004