Intel IXF1104 manual TX Fifo Registers $ 0x600 0x63E Sheet 2, Mdio Registers $ 0x680

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 65. TX FIFO Registers ($ 0x600 - 0x63E) (Sheet 2 of 2)

Register	Bit Size	Mode1	Ref Page	Address
Reserved	32	RO	–	0x60E - 0x613
TX FIFO MAC Threshold Port 0	32	R/W	204	0x614
TX FIFO MAC Threshold Port 1	32	R/W	204	0x615
TX FIFO MAC Threshold Port 2	32	R/W	204	0x616
TX FIFO MAC Threshold Port 3	32	R/W	204	0x617
Reserved	–	RO	–	0x618 - 0x61D
TX FIFO Overflow/Underflow Event/Out of Sequence	32	R	205	0x61E
Loop RX Data to TX FIFO	32	R/W	206	0x61F
TX FIFO Port Reset	32	R/W	206	0x620
TX FIFO Overflow Frame Drop Counter Port 0	32	R	207	0x621
TX FIFO Overflow Frame Drop Counter Port 1	32	R	207	0x622
TX FIFO Overflow Frame Drop Counter Port 2	32	R	207	0x623
TX FIFO Overflow Frame Drop Counter Port 3	32	R	207	0x624
TX FIFO Errored Frame Drop Counter Port 0	32	R	208	0x625
TX FIFO Errored Frame Drop Counter Port 1	32	R	208	0x626
TX FIFO Errored Frame Drop Counter Port 2	32	R	208	0x627
TX FIFO Errored Frame Drop Counter Port 3	32	R	208	0x628
Reserved	32	R	–	0x629 - 0x62C
TX FIFO Occupancy Counter for Port 0	32	R	209	0x62D
TX FIFO Occupancy Counter for Port 1	32	R	209	0x62E
TX FIFO Occupancy Counter for Port 2	32	R	209	0x62F
TX FIFO Occupancy Counter for Port 3	32	R	209	0x630
Reserved	32	R	–	0x631 - 0x63E

Table 66. MDIO Registers ($ 0x680 - 0x683)

Register	Bit Size	Mode1	Ref Page	Address
“MDIO Single Command ($0x680)”	32	R/W	210	0x680
“MDIO Single Read and Write Data ($0x681)”	32	R/W	210	0x681
“Autoscan PHY Address Enable ($0x682)”	32	R/W	211	0x682
“MDIO Control ($0x683)”	32	R/W	211	0x683

Table 67. SPI3 Registers ($ 0x700 - 0x716) (Sheet 1 of 2)

Register	Bit Size	Mode1	Ref Page	Address
“SPI3 Transmit and Global Configuration ($0x700)”	32	R/W	212	0x700
“SPI3 Receive Configuration ($0x701)”	32	R/W	214	0x701

160 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004