Intel IXF1104 5.6.2.6Transmit Jitter, 5.6.2.7Receive Jitter, Sinusoidal Jitter Mask, Frequency

Models: IXF1104

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Sinusoidal Jitter Mask

IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller

Figure 23. SerDes Receiver Jitter Tolerance

Sinusoidal Jitter Mask

 

 

16 ui

 

375 Hz 16 ui

 

 

 

 

 

 

 

 

 

 

 

10+1

 

 

 

 

22.5836 kHz 8.5 ui

 

 

 

 

 

 

 

 

(UI)

 

 

 

 

 

 

 

 

Peak-to-Peak Amplitude

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10-1

 

 

 

 

1.9195 MHz 0.1 ui

 

 

100

101

102

103

104

105

106

107

 

 

 

 

Frequency

 

 

 

 

 

 

 

 

 

 

 

B0745-02

Note: UI = Unit interval.

5.6.2.6Transmit Jitter

The SerDes core total transmit jitter, including contributions from the intermediate frequency PLL, is comprised of the following two components:

A deterministic component attributed to the SerDes core’s architectural characteristics

A random component attributed to random thermal noise effects

Since the thermal noise component is random and statistical in nature, the SerDes core total transmit jitter must be specified as a function of BER.

5.6.2.7Receive Jitter

The SerDes core total receiver jitter, including contributions from the intermediate frequency PLL, is comprised of the following two components:

A deterministic component attributed to the SerDes core architectural characteristics

A random component attributed to random thermal noise effects.

Datasheet

105

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Page 105
Image 105
Intel IXF1104 5.6.2.6Transmit Jitter, 5.6.2.7Receive Jitter, Sinusoidal Jitter Mask, Peak-to-PeakAmplitude, Frequency