Intel IXF1104 manual Product Features, Datasheet

Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004

Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller

Datasheet

The Intel® IXF1104 is a four-port Gigabit MAC that supports IEEE 802.3 10/100/1000 Mbps applications. The IXF1104 supports a System Packet Interface Phase 3 (SPI3) system interface to a network processor or ASIC, and concurrently supports copper and fiber physical layer devices (PHYs).

The copper PHY interface implements the Gigabit Media Independent Interface (GMII) and the Reduced Gigabit Media Independent Interface (RGMII) as defined in Version 1.2a of the Hewlett-Packard* specification. RGMII has the benefit of reducing the PHY interface pin count for high-port-count applications.

The fiber PHY interface implements an internal Serializer/Deserializer (SerDes) on each port to allow direct connection to optical modules. The integration of the SerDes functionality reduces PCB area requirements and system cost.

Product Features

4 Independent Ethernet MAC Ports which		￿	Programmable Packet handling
support 3 interfaces for Copper or Fiber			— Filter packets with errors
Physical layer connectivity.
			— Filter broadcast, multicast, unicast and
—IEEE 802.3 compliant
			VLAN packets
—RMON Statistics
			— Automatically pad transmitted packets
—Independent Enable/Disable of any port
			less than the minimum frame size
Copper Mode:			— Remove CRC from packets received
—RGMII for 10/100/1000 Mbps			Performance Monitoring and Diagnostics
connections
			— CRC calculation and error detection
—GMII for 1000 Mbps full-duplex
			— Detection of length error, runt or overly
connectivity
			large packets
￿—IEEE 802.3 MDIO interface
			— Counters for dropped and errored
Fiber Mode:			packets
—Integrated SerDes interface for direct			— Loopback modes
connection to optical modules for
			— JTAG- and boundary-scan-capable
1000BASE-X connectivity
			IEEE 802.3 Complaint Flow Control
—Supports IEEE 802.3 fiber auto-
			— Loss-less flow control for up to 9.6 KB
negotiation including forced mode
			packets and 5 km of fiber
—Small Form Factor Pluggable (SFP)
			— Jumbo frame support for 9.6 KB packets
Transceiver MSA compatible
System Packet Interface Level 3 (SPI3)		￿￿	Internal 32 KB receive FIFO and 10 KB
			transmit FIFOs per channel
—Capable of data transfers at 4 Gbps in
			552-ball Ceramic Ball Grid Array (CBGA)
both SPI3 modes:
			— 1.8 V core, 2.5 V RGMII, GMII, OMI,
32-bit Multi-PHY mode (133 Mhz)
4 x 8bit Single-PHY mode (125 Mhz)			and 3.3 V SPI3 and CPU
Operating Temperature Ranges:			— .18 ∝ CMOS process technology
MIN	MAX		Product Ordering Number:
Copper Mode: -40°C	+85°C		HFIXF1104CE.B0 853714

￿Fiber Mode: 0°C +70°C

Flexible 32/16/8-bit CPU interface