Intel IXF1104 manual 4.2Interface Signal Groups, Datasheet, Sphy Mphy, Gmii, Rgmii

IXF1104 4-Port Gigabit Ethernet Media Access Controller

4.2Interface Signal Groups

This section describes the IXF1104 signals in groups according to the associated interface or function. Figure 4 shows the various interfaces available on the IXF1104.

Figure 4. Interface Signals

SPI3 Interface

JTA G Interface

MDIO Interface

Pause

Control

Interface

CPU Interface

LED Interface

SPHY MPHY

TDAT[7:0]_0:3 TDAT[31:0]

TFCLK TFCLK

TENB_0:3 TEN B_0

TERR _0:3 TER R_0

TPRTY_0:3 TPRTY_0 TMOD [1:0]

TSX

TSOP_0:3 TSOP_0

TEOP_0:3 TEOP_0

TADR[1:0] TADR [1:0]

DTPA_0:3 DTPA_0:3

STPA

PTPA PTPA

RDAT[7:0]_0:3 R D AT[31:0]

RFCLK RFCLK

RENB_0:3 R EN B_0

RVAL_0:3 R VAL_0

RERR _0:3 R ER R _0

RPRTY_0:3 RPRTY_0 RMOD [1:0]

RSX

RSOP_0:3 R SOP_0

REOP_0:3 R EOP_0

TMS

TD I

TD O

TCLK

TRST_L

MDIO

MD C

TXPAUSEADD [2:0]

TXPAUSEFR

UPX_WID TH [1:0] UPX_D ATA[31:0] U PX_AD D[10:0] U PX_BADD [1:0] U PX_WR_L U PX_R D_L U PX_C S_L U PX_RD Y_L

LED_CLK

LED _D ATA

LED_LATCH

Intel® IXF1104

Media Access

Controller

GMII	RGMII
TXC_0:3	TXC _0:3
TXD[7:0]_0	TD[3:0]_0
TXD[7:0]_1	TD[3:0]_1
TXD[7:0]_2	TD[3:0]_2
TXD[7:0]_3	TD[3:0]_3
TX_EN_0:3	TX_CTL_0:3
TX_ER_0:3
RXC_0:3	RXC _0:3	GMII and
RXD[7:0]_3	RD[3:0]_0
		RGMII
RXD[7:0]_2	RD[3:0]_1
		Interfaces*
RXD[7:0]_1	RD[3:0]_2
RXD[7:0]_0	RD[3:0]_3
RX_DV_0:3	RX_CTL_0:3
RX_ER_0:3
CRS_0:3
COL_0:3

*Data and clock balls are shared for GMII and RGMII Interfaces

		RX_P/N_0:3	SerDes
		TX_P/N_0:3	Interface
		TX_D ISABLE_0:3
		MOD _DEF_0:3
		TX_FAU LT_0:3	Optical
		RX_LOS_0:3
			Module
		TX_FAU LT_IN T
			Interface
		RX_LOS_IN T
			Signals*
		MOD _DEF_IN T
			*
		I2 C _C LK
		I2 C _D ATA_0:3
** These optical module signals
	are multiplexed on the GMII balls.
			System
		SYS_RES_L
		CLK125	Interface

B3181-01

Datasheet 37

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004