IXF1104
Table 47. SPI3 Transmit Interface Signal Parameters
Symbol | Parameter | Min | Max | Units |
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– | TFCLK frequency | – | 133 | MHz |
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– | TFCLK duty cycle | 40 | 60 | % |
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TStenb | TENB setup time to TFCLK | 1.8 | – | ns |
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THtenb | TENB hold time to TFCLK | 0.5 | – | ns |
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TStdat | TDAT[31:0] setup time to TFCLK | 1.8 | – | ns |
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THtdat | TDAT[31:0} hold time to TFCLK | 0.5 | – | ns |
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TStprty | TRPTY setup time to TFCLK | 1.8 | – | ns |
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THtprty | TPRTY hold time to TFCLK | 0.5 | – | ns |
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TStsop | TSOP setup time to TFCLK | 1.8 | – | ns |
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THtsop | TSOP hold time to TFCLK | 0.5 | – | ns |
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TSteop | TEOP setup time to TFCLK | 1.8 | – | ns |
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THteop | TEOP hold time to TFCLK | 0.5 | – | ns |
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TStmod | TMOD setup time to TFCLK | 1.8 | – | ns |
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THtmod | TMOD hold time to TFCLK | 0.5 | – | ns |
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TSterr | TERR setup time to TFCLK | 1.8 | – | ns |
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THterr | TERR hold time to TFCLK | 0.5 | – | ns |
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TStsx | TSX setup time to TFCLK | 1.8 | – | ns |
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THtsx | TSX hold time to TFCLK | 0.5 | – | ns |
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TStadr | TADR setup time to TFCLK | 1.8 | – | ns |
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THtadr | TADR hold time to TFCLK | 0.5 | – | ns |
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TPdtpa | TFCLK High to DTPA valid | 1.5 | 3.7 | ns |
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TPstpa | TFCLK High to STPA valid | 1.5 | 3.7 | ns |
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TPptpa | TFCLK High to PTPA valid | 1.5 | 3.7 | ns |
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NOTES:Transmit I/O Timing:
1. When a setup time is specified between an input and a clock, the setup time is the time in nanoseconds from the 1.4 V point of the input to the
2. When a hold time is specified between an input and clock, the hold time is the time in nanoseconds from the 1.4 V point of the clock to the
3. Output propagation delay time is the time in nanoseconds from the 1.4 V point of the reference signal to the 1.4 V point of the output.
Datasheet | 139 |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004