Intel IXF1104 manual Datasheet

Models: IXF1104

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IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 135. TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) (Sheet 2 of 2)

Bit

Name

Description

Type1

Default

 

 

 

 

 

 

 

Port 2

 

 

2

FOE2

0 = FIFO overflow event did not occur

R

0

 

 

1 = FIFO overflow event occurred

 

 

 

 

 

 

 

 

 

Port 1

 

 

1

FOE1

0 = FIFO overflow event did not occur

R

0

 

 

1 = FIFO overflow event occurred

 

 

 

 

 

 

 

 

 

Port 0

 

 

0

FOE0

0 = FIFO overflow event did not occur

R

0

 

 

1 = FIFO overflow event occurred

 

 

 

 

 

 

 

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Table 136. Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)

Bit

Name

Description

 

Type1

Default

 

 

 

 

 

Register Description: This register enables data received from the line-side receive interface

0x00000000

through the MAC to be sent to the TX FIFO and back to the line-side transmit interface.

 

 

 

 

 

 

 

 

 

31:4

Reserved

Reserved

 

RO

0x0000000

 

 

 

 

 

 

 

3

Port 3 Line-Side

0 =

Disable line-side loopback

 

R/W

0

Loopback

1 =

Enable line-side loopback

 

 

 

 

 

 

 

 

 

 

 

 

2

Port 2 Line-Side

0 =

Disable line-side loopback

 

R/W

0

Loopback

1 =

Enable line-side loopback

 

 

 

 

 

 

 

 

 

 

 

 

1

Port 1 Line-Side

0 =

Disable line-side loopback

 

R/W

0

Loopback

1 =

Enable line-side loopback

 

 

 

 

 

 

 

 

 

 

 

 

0

Port 0 Line-Side

0 =

Disable line-side loopback

 

R/W

0

Loopback

1 =

Enable line-side loopback

 

 

 

 

 

 

 

 

 

 

 

 

1.RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Table 137. TX FIFO Port Reset ($0x620) (Sheet 1 of 2)

Bit

Name

Description

Type1

Default

 

 

 

 

 

Register Description: This is a port reset register for each port in the TX block. Port ID = bit

 

position in the register. To make the port active, the bit must be set to Low. (For example, reset

0x00000000

of Port 3 implies register value = 1000, setting the bit to 1 asserts the port reset).

 

 

 

 

 

 

 

31:4

Reserved

Reserved

RO

0x0000000

 

 

 

 

 

 

 

 

Port

3

 

 

3

Port 3 Reset

0 =

De-assert Reset

R/W

0

 

 

1 =

Assert Reset

 

 

 

 

 

 

 

 

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

206

Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Page 206
Image 206
Intel IXF1104 manual Datasheet