IXF1104
Table 135. TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) (Sheet 2 of 2)
Bit | Name | Description | Type1 | Default |
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| Port 2 |
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2 | FOE2 | 0 = FIFO overflow event did not occur | R | 0 |
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| 1 = FIFO overflow event occurred |
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| Port 1 |
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1 | FOE1 | 0 = FIFO overflow event did not occur | R | 0 |
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| 1 = FIFO overflow event occurred |
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| Port 0 |
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0 | FOE0 | 0 = FIFO overflow event did not occur | R | 0 |
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| 1 = FIFO overflow event occurred |
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1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
Table 136. Loop RX Data to TX FIFO
Bit | Name | Description |
| Type1 | Default | |
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Register Description: This register enables data received from the | 0x00000000 | |||||
through the MAC to be sent to the TX FIFO and back to the |
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31:4 | Reserved | Reserved |
| RO | 0x0000000 | |
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3 | Port 3 | 0 = | Disable |
| R/W | 0 |
Loopback | 1 = | Enable |
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2 | Port 2 | 0 = | Disable |
| R/W | 0 |
Loopback | 1 = | Enable |
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1 | Port 1 | 0 = | Disable |
| R/W | 0 |
Loopback | 1 = | Enable |
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0 | Port 0 | 0 = | Disable |
| R/W | 0 |
Loopback | 1 = | Enable |
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1.RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
Table 137. TX FIFO Port Reset ($0x620) (Sheet 1 of 2)
Bit | Name | Description | Type1 | Default | |
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Register Description: This is a port reset register for each port in the TX block. Port ID = bit |
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position in the register. To make the port active, the bit must be set to Low. (For example, reset | 0x00000000 | ||||
of Port 3 implies register value = 1000, setting the bit to 1 asserts the port reset). |
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31:4 | Reserved | Reserved | RO | 0x0000000 | |
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| Port | 3 |
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3 | Port 3 Reset | 0 = | R/W | 0 | |
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| 1 = | Assert Reset |
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1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
206 | Datasheet |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004