IXF1104
5.2.2.1Transmit Timing
In MPHY mode a packet transmission starts with the TSX signal indicating port address information is on the data bus. The next clock cycle TENB and TSOP indicate present data on the bus is the first word in the packet and all subsequent clocks will contain valid data as long as TENB is active or until TEOP is asserted. Data transmission can be temporally halted when TENB goes high then resumed when TENB is low. The valid bytes in the final word, during an active TEOP, are indicated by state of TMOD [1:0].
Figure 11. MPHY Transmit Logical Timing
TFCLK |
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TENB |
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TSOP |
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TEOP |
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TMOD[1:0] |
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TERR |
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TSX |
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TDAT[31:0] | 0000 |
TPRTY
TPA1
1.Applies to all transmit packet available signals (STPA, PTPA, DTPA_0:3).
5.2.2.2Receive Timing
A packet is received when RSX indicates port address information on the data bus followed by RSOP to indicate the data bus contains the first word of a packet. All subsequent data is valid only while RVAL is High and until REOP is asserted. Receive data can be temporarily halted when RENB is
84 | Datasheet |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004