Intel IXF1104 manual Datasheet, Receive Data Bus, Mode, Bits, Receive Clock, Receive Parity

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 3. SPI3 Interface Signal Descriptions (Sheet 6 of 8)

Signal Name		Ball	Type	Standard	Description
MPHY	SPHY	Designator
RDAT7	RDAT7_0	F14			Receive Data Bus.
RDAT6	RDAT6_0	E14			RDAT carries payload data and in-band
RDAT5	RDAT5_0	D14
				3.3 V	addresses from the IXF1104.
RDAT4	RDAT4_0	C13
			Output
RDAT3	RDAT3_0	C14		LVTTL	Mode	Bits
RDAT2	RDAT2_0	B14			32-bit Multi-PHY	[7:0]
RDAT1	RDAT1_0	A14
					4 x 8 Single-PHY	[7:0] for port 0
RDAT0	RDAT0_0	A15
					Receive Clock.
RFCLK	RFCLK	A19	Input	3.3 V	RFCLK is the clock associated with all
					receive signals. Data and controls are
				LVTTL
					driven on the rising edge of RFCLK
					(frequency operation range 90 - 133 MHz).
					Receive Parity.
					RPRTY indicates odd parity for the RDAT
					bus. RPRTY is valid only when a channel
					asserts RENB or RSX. Odd parity is the
RPRTY_0	RPRTY_0	E15			default configuration; however, even parity
	RPRTY_1	G16	Output	3.3 V	can be selected (see Table 147 on
	RPRTY_2	E20		LVTTL	page 214).
	RPRTY_3	F20			32-bit Multi-PHY mode: RPRTY_0 is the
					parity bit for all 32 bits.
					4 x 8 Single-PHY mode: Each bit of
					RPRTY_0:3 corresponds to the respective
					RDAT[3:0]_n channel.
					Receive Read Enable.
					The RENB signal controls the flow of data
					from the receive FIFOs. During data
					transfer, RVAL must be monitored as it
					indicates if the RDAT[31:0], RPRTY,
					RMOD[1:0], RSOP, REOP, RERR, and RSX
					are valid. The system may de-assert RENB
					at any time if it is unable to accept data from
					the IXF1104. When RENB is sampled Low,
					a read is performed from the receive FIFO
RENB_0	RENB_0	A13			and the RDAT[31:0], RPRTY, RMOD[1:0],
				3.3 V	RSOP, REOP, RERR, RSX and RVAL
	RENB_1	A18	Input		signals are updated on the following rising
	RENB_2	C19		LVTTL	edge of RFCLK.
	RENB_3	E24			When RENB is sampled High by the PHY
					device, a read is not performed, and the
					RDAT[31:0], RPRTY, RMOD[1:0], RSOP,
					REOP, RERR, RSX, and RVAL signals
					remain unchanged on the following rising
					edge of RFCLK.
					32-bit Multi-PHY Mode: RENB_0 covers all
					receive bits.
					4 x 8 Single-PHY Mode: The RENB_0:3
					bits correspond to the per-port data and
					control signals.

Datasheet 43

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004