IXF1104
5.1.8.2IXF1104 Advantages
The following lists additional IXF1104 registers that support features not documented in RMON:
•MAC (flow) control frames
•VLAN Tagged
•Sequence Errors
•Symbol Errors
•CRC Error
These additional counters allow for differentiation beyond standard RMON probes.
Note: In fiber mode, a packet transfer with an invalid
•Behavior: The IXF1104 8B10B decoder substitutes a valid code word octet in its place. The packet transfer is aborted and marked as bad. The new internal length of the packet is equal to the byte position where the invalid symbol was. No packet fragments are seen at the next packet transfer.
•Issue: If the invalid
5.2SPI3 Interface
The IXF1104 SPI3 Interface is implemented to the System Packet Interface Level 3 (SPI3) Physical Layer Interface standard. The interface function allows the IXF1104 MAC blocks to interface to
The transmit interface allows data flows from a network processor or switch fabric device to the IXF1104. The receive interface allows data to flow from the IXF1104 to the network processor or switch fabric device.
This interface receives and transmits data between the MAC and the Network Processor with compliant SPI3 interfaces. The SPI3 interface operation is defined in the
There is no guarantee of the number of bytes available since the size of packets is variable. An IXF1104
In the receive direction, RVAL indicates if valid data is available on the receive data bus and is defined so that data transfers can be aligned with packet boundaries.
The SPI3 interface supports the following two modes of operation:
•MPHY or 32 bit mode (one
82 | Datasheet |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004