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Intel IXF1104 manual 2.0General Description, Datasheet

Models: IXF1104

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IXF1104 4-Port Gigabit Ethernet Media Access Controller

2.0General Description

The IXF1104 provides up to a 4.0 Gbps interface to four individual 10/100/1000 Mbps full-duplex or 10/100 Mbps half-duplex-capable Ethernet Media Access Controllers (MACs). The network processor is supported through a System Packet Interface Phase 3 (SPI3) media interface. The following PHY interfaces are selected on a per-port basis:

•Serializer/Deserializer (SerDes) with Optical Module Interface support

•Gigabit Media Independent Interface (GMII)

•Reduced Gigabit Media Independent Interface (RGMII).

Figure 1 illustrates the IXF1104 block diagram.

Figure 1. Block Diagram

		CPU
		uP IF
Processor			Interface	PHY 1 Device
Processor			Interface
Forwarding Engine/Network			SerDes/RGMII/GMII	PHY 2 Device
		Intel®
	SPI3	IXF1104 MAC
	SPI3			PHY 3 Device
				PHY 3 Device
				PHY 4 Device

		MDIO
				B3175-01

Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

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Intel IXF1104 manual 2.0General Description, Datasheet

Contents

Product Features DatasheetDatasheet ApplicationsContents IntroductionContents DatasheetContents DatasheetContents DatasheetDatasheet ApplicationsContents Figures 10.0Contents DatasheetDatasheet TablesContents Contents DatasheetContents DatasheetContents DatasheetDatasheet Revision HistoryContents Contents DatasheetRevision Number: Revision Date: March 25,Contents DatasheetContents DatasheetRevision Number: Revision Date: March 25, Sheet 4 of Page # DescriptionContents DatasheetRevision Number: Revision Date: March 25, Sheet 5 ofContents DatasheetContents Datasheet1.0Introduction 1.1What You Will Find in This Document1.2Related Documents Datasheet2.0General Description DatasheetDatasheet Figure 2. Internal Architecture3.0Ball Assignments and Ball List Tables 3.1Ball AssignmentsDatasheet = No Pad A13.Fiber Mode Ball Connection 3.2Ball List Tables1.GMII Ball Connection 2.SPI3 Ball ConnectionDatasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Revision Date: March 25, DatasheetDocument Number: Revision Number: 4.0Ball Assignments and Signal Descriptions 4.1Naming Conventions4.1.1Signal Name Conventions Datasheet4.2Interface Signal Groups DatasheetSPHY MPHY GMII4.3Signal Description Tables DatasheetMode BitsDatasheet Transmit Write EnableTransmit Error Transmit ParityDatasheet TMOD1:0 Transmit Word Modulo32-bit Multi-PHYmode: TMOD1:0 4 x 8 Single-PHYmode: MOD1:0 is notAvailable DatasheetDTPA_0:3 Direct Transmit Packet Datasheet Polled-PHYTransmit Packet AvailableReceive Data Bus ModeDatasheet Receive Read EnableReceive Data Bus ModeDatasheet Receive Error32-bit Multi-PHYmode: RERR_0 covers 4 x 8 Single-PHYmode: The RERR_0:3Datasheet Receive End of Packet32-bit Multi-PHYmode: REOP_0 covers 4 x 8 Single-PHYmode: The REOP_0:3Table 4. SerDes Interface Signal Descriptions DatasheetDatasheet Transmit EnableTransmit Error Transmit DataDatasheet Receive ErrorReceive Data Receive Data ValidDatasheet Source Synchronous Transmit ClockTransmit Data Transmit ControlReceive Control DatasheetReceive Data Datasheet Cycle complete indicatorData bus 32-bitmode: Uses 31:0Receiver Loss of Signal Interrupt DatasheetTransmit Disable Table 10. MDIO Interface Signal Descriptions DatasheetTransmitter Fault Interrupt Module Definition InterruptTable 11. LED Interface Signal Descriptions Table 12. JTAG Interface Signal DescriptionsTable 13. System Interface Signal Descriptions DatasheetTable 14. Power Supply Signal Descriptions DatasheetTotal 4.4Ball Usage SummaryDatasheet 4.5Multiplexed Ball Connections Datasheet4.5.2SPI3 MPHY/SPHY Ball Connections DatasheetDatasheet Table 17. SPI3 MPHY/SPHY Interface Sheet 2 of4.6Ball State During Reset DatasheetDatasheet 4.7Power Supply Sequencing 4.7.1Power-UpSequence4.7.2Power-DownSequence DatasheetDatasheet 4.9Analog Power Filtering4.8Pull-Up/Pull-DownBall Guidelines Power Ball Datasheet2.5 or 1.8 AnalogDatasheet 5.1Media Access Controller MAC5.0Functional Descriptions 5.1.1Features for Fiber and Copper Mode 5.1.1.1Padding of Undersized Frames on Transmit5.1.1.2Automatic CRC Generation 5.1.1.3Filtering of Receive Packets5.1.1.3.6Filter CRC Error Packets 5.1.1.3.2Filter on Multicast Packet Match5.1.1.3.3Filter Broadcast Packets 5.1.1.3.4Filter VLAN PacketsDatasheet 5.1.1.4CRC Error Detection5.1.2Flow Control 5.1.2.1802.3x Flow Control Full-DuplexOperation DatasheetDatasheet 5.1.2.1.1Pause Frame FormatSPI3 Interface 5.1.2.1.2Pause Settings DatasheetDatasheet 5.1.2.1.4Half-DuplexOperation5.1.2.1.5Transmit Pause Control Interface “FC TX Timer Value $ Port_Index + 0x07 XOFF “FC TX Timer Value $ Port_Index + 0x07 XOFF“FC TX Timer Value $ Port_Index + 0x07 XOFF “FC TX Timer Value $ Port_Index + 0x07 XOFF5.1.3.1Configuration of the IXF1104 5.1.3.2Key Configuration Registers5.1.3Mixed-ModeOperation Datasheet5.1.4Fiber Mode Datasheet5.1.5Copper Mode 5.1.4.3Fiber Forced Mode5.1.4.1Fiber Auto-Negotiation Datasheet5.1.6Jumbo Packet Support 5.1.5.1Speed5.1.5.2Duplex 5.1.5.3Copper Auto-Negotiation5.1.6.1Rx Statistics 5.1.6.2TX Statistics5.1.6.3Loss-lessFlow Control Datasheet5.1.7Packet Buffer Dimensions 5.1.8RMON Statistics Support5.1.7.1TX and RX FIFO Operation 5.1.7.1.1TX FIFO 5.1.7.1.2RX FIFODatasheet Table 25. RMON Additional Statistics Sheet 1 of5.1.8.1Conventions DatasheetDatasheet 5.2SPI3 Interface5.1.8.2IXF1104 Advantages 5.2.1MPHY Operation 5.2.2MPHY Logical TimingData Path 5.2.1.1SPI3 RX Round Robin Data TransmissionDatasheet 5.2.2.1Transmit Timing5.2.2.2Receive Timing Datasheet Network ProcessorIXF1104 MPHY Line-SideInterface5.2.2.5SPHY Mode 5.2.2.3Clock Rates5.2.2.4Parity 5.2.2.5.1Data Path5.2.2.6SPHY Logical Timing 5.2.2.7Transmit Timing SPHY5.2.2.8Receive Timing SPHY DatasheetDatasheet Figure 15. SPHY Receive Logical Timing5.2.2.8.1Clock Rates Datasheet5.2.2.8.2Parity 5.2.2.9SPI3 Flow Control5.2.2.9.1RX SPI3 Flow Control 5.2.2.9.2TX SPI3 Flow ControlDTPA_0:3 STPAPTPA DatasheetDatasheet 5.3Gigabit Media Independent Interface GMII5.2.3Pre-PendingFunction Datasheet 5.3.1GMII Signal Multiplexing5.3.2GMII Interface Signal Definition Datasheet Transmit EnableTransmit Error Receive ErrorMedia Access Controller 5.4.1Multiplexing of Data and ControlIntel IXF1104 Quad PHY DeviceDatasheet 5.4.2Timing Specifics5.4.3TX_ER and RX_ER Coding Datasheet TXC_0:3TD3:0_0:3 TX_CTL_0:35.5MDIO Control and Interface 5.4.410/100 Mbps Functionality5.4.3.1In-BandStatus Datasheet5.5.3Clear When Done 5.5.1MDIO Address5.5.2MDIO Register Descriptions 5.5.4MDC Generation5.5.6Single MDI Command Operation 5.5.5Management Frames5.5.7MDI State Machine DatasheetDatasheet Figure 22. MDI State5.6.1Features 5.6SerDes Interface5.5.8Autoscan Operation 5.6.2Functional Description5.6.2.1Transmitter Operational Overview Datasheet5.6.2.4Selective Power-Down 5.6.2.3Receiver Operational Overview5.6.2.5Receiver Jitter Tolerance Datasheet5.6.2.6Transmit Jitter 5.6.2.7Receive JitterDatasheet Sinusoidal Jitter Mask5.7Optical Module Interface Datasheet5.7.2.2Low-SpeedStatus Signaling Interface 5.7.2Functional Descriptions5.7.2.1High-SpeedSerial Interface 5.7.2.2.1MOD_DEF_0:35.7.2.2.2TX_FAULT_0:3 5.7.2.2.4TX_DISABLE_0:35.7.2.2.6TX_FAULT_INT 5.7.2.2.3RX_LOS_0:35.7.3I²C Module Configuration Interface 5.7.3.1I2C Control and Data Registers5.7.3.2I2C Read Operation •“I2C Control Ports 0 - 3 $0x79B” on page5.7.3.3I2C Write Operation Datasheet5.7.3.4I²C Protocol Specifics 5.7.3.5Port Protocol Operation5.7.3.6Clock and Data Transitions Datasheet5.7.3.6.1Start Condition 5.7.3.6.2Stop Condition5.7.3.6.3Acknowledge Datasheet5.7.3.6.4Memory Reset 5.7.3.6.5Device Addressing5.7.3.6.6Random Read Operation Datasheet5.8.2LED Interface Signal Description 5.8LED Interface5.8.1Modes of Operation Datasheet5.8.3Mode 0: Detailed Operation Datasheet5.8.4Mode 1: Detailed Operation DatasheetDatasheet 5.8.5Power-On,Reset, Initialization5.8.6LED DATA Decodes Datasheet 5.8.6.1LED Signaling Behavior5.8.6.1.1 Fiber LED Behavior Datasheet 5.9CPU Interface5.8.6.1.2Copper LED Behavior 5.9.1.1Read Access 5.9.1.2Write Access5.9.1Functional Description DatasheetDatasheet 5.9.2Endian5.9.1.3CPU Timing Parameters Datasheet 5.10TAP Interface JTAG5.10.1TAP State Machine Datasheet Table 38. Instruction Register Description5.11Loopback Modes 5.10.3ID Register5.10.4Boundary Scan Register 5.10.5Bypass Register5.11.2Line Side Interface Loopback DatasheetDatasheet 5.12Clocks5.12.1System Interface Reference Clocks 5.12.2SPI3 Receive and Transmit Clocks 5.12.3RGMII Clocks5.12.4MDC Clock 5.12.1.1CLK1255.12.5JTAG Clock 5.12.6I2C Clock5.12.7LED Clock DatasheetDatasheet 6.1Change Port Mode Initialization Sequence6.0Applications 13.Assert set to 1 “Port Enable $0x500” Datasheet7.0Electrical Specifications Datasheet7.1DC Specifications DatasheetTable 41. Intel IXF1104 MAC DC Specifications DatasheetDatasheet 7.1.1Undershoot / Overshoot Specifications7.1.2RGMII Electrical Characteristics Table 45. RGMII Power DatasheetDatasheet 7.2SPI3 AC Timing Specifications7.2.1Receive Interface Timing Datasheet 7.2.2Transmit Interface Timing DatasheetDatasheet 7.3RGMII AC Timing Specification Datasheet7.4GMII AC Timing Specification 7.4.11000 Base-TOperation7.4.1.11000 BASE-TTransmit Interface Datasheet7.4.1.21000BASE-TReceive Interface Datasheet7.5SerDes AC Timing Specification Datasheet7.6MDIO AC Timing Specification 7.6.1MDC High-SpeedOperation Timing7.6.2MDC Low-SpeedOperation Timing Datasheet7.6.3MDIO AC Timing DatasheetMDIO MDC MDIODatasheet 7.7Optical Module and I2C AC Timing Specification7.7.1I2C Interface Timing Datasheet 7.8CPU AC Timing Specification 7.8.1CPU Interface Read Cycle AC Timing7.8.2CPU Interface Write Cycle AC Timing DatasheetDatasheet 7.9Transmit Pause Control AC Timing Specification Datasheet7.10JTAG AC Timing Specification Datasheet7.11System AC Timing Specification Datasheet7.12LED AC Timing Specification Datasheet8.0Register Set 8.1Document Structure8.2Graphical Representation DatasheetDatasheet 8.3Per Port Registers8.4Register Map Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Table 68. SerDes Registers $ 0x780 -8.4.1MAC Control Registers DatasheetSource MAC address bit Source MAC address bitTable 75. FC TX Timer Value $ Port_Index + DatasheetTable 73. Collision Distance $ Port_Index + Table 74. Collision Threshold $ Port_Index +Datasheet Table 77. IPG Receive Time 1 $ Port_Index + 0x0ATable 78. IPG Receive Time 2 $ Port_Index + 0x0B Table 79. IPG Transmit Time $ Port_Index + 0x0CTable 81. Max Frame Size Addr: Port_Index + 0x0F DatasheetTable 80. Pause Threshold $ Port_Index + 0x0E Datasheet Table 83. Flush TX $ Port_Index +Table 85. FC Back Pressure Length $ Port_Index + Table 84. FC Enable $ Port_Index +Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet 8.4.2MAC RX Statistics Register Overview DatasheetDatasheet Datasheet Datasheet 8.4.3MAC TX Statistics Register Overview DatasheetDatasheet Datasheet 8.4.4PHY Autoscan Registers DatasheetDatasheet Datasheet Datasheet Datasheet Datasheet Datasheet Datasheet Table 103. Port Enable $0x500Table 104. Interface Mode $0x501 Datasheet Table 105. Link LED Enable $0x502Table 106. MAC Soft Reset $0x505 Table 107. MDIO Soft Reset $0x506 DatasheetTable 108. CPU Interface $0x508 Table 109. LED Control $0x509Table 110. LED Flash Rate $0x50A Table 111. LED Fault Disable $0x50BDatasheet Datasheet Table 112. JTAG ID $0x50C8.4.6RX FIFO Register Overview DatasheetDatasheet Table 116. RX FIFO High Watermark Port 3 $0x583Table 117. RX FIFO Low Watermark Port 0 $0x58A Table 118. RX FIFO Low Watermark Port 1 $0x58BTable 120. RX FIFO Low Watermark Port 3 $0x58D DatasheetTable 119. RX FIFO Low Watermark Port 2 $0x58C Table 122. RX FIFO Port Reset $0x59E DatasheetDatasheet Table 124. RX FIFO Overflow Event $0x5A0with the“RX FIFO Errored Frame Drop Enable $0x59F” and the “RXPacket Filter Control $ Port_Index + 0x19”with the“RX FIFO Errored Frame Drop Enable $0x59F” and the “RXwith the“RX FIFO Errored Frame Drop Enable $0x59F” and the “RXDatasheet Datasheet Datasheet 8.4.7TX FIFO Register Overview DatasheetHigh watermark for TX FIFO Port 0. The High watermark for TX FIFO Port 1. TheDatasheet Low watermark for TX FIFO Port 0. TheLow watermark for TX FIFO Port 1. The Low watermark for TX FIFO Port 2. TheDatasheet MAC threshold for TX FIFO Port 0. TheMAC threshold for TX FIFO Port 1. The MAC threshold for TX FIFO Port 2. TheRegister Description: TX FIFO Overflow Event DatasheetRegister Description: TX FIFO Underflow Event Datasheet Table 137. TX FIFO Port Reset $0x620 Sheet 2 of DatasheetDatasheet Table 141. TX FIFO Port Drop Enable $0x63D Datasheet8.4.8MDIO Register Overview DatasheetTable 145. MDIO Control $0x683 Table 144. Autoscan PHY Address Enable $0x682Datasheet 8.4.9SPI3 Register Overview DatasheetSPHY/MPHY Mode SPHY/MPHY ModeDatasheet SPHY/MPHY ModeSPHY Mode MPHY ModeDatasheet SPHY ModeMPHY Mode SPHY ModeDatasheet SPHY ModeMPHY Mode SPHY ModeDatasheet SPHY ModeMPHY Mode SPHY ModeDatasheet SPHY ModeMPHY Mode SPHY ModeDatasheet 8.4.10SerDes Register Overview DatasheetDatasheet 8.4.11Optical Module Register Overview DatasheetTable 156. I2C Data Ports 0 - 3 $0x79F DatasheetTable 155. I2C Control Ports 0 - 3 $0x79B 9.0Mechanical Specifications 9.1.1Features9.1Overview 9.2Package Specifics for the IXF11049.3Package Information Datasheet= Ball = No ballFigure 56. CBGA Package Side View Diagram Datasheet9.3.1Example Package Marking DatasheetSyww9001 Pin 1 mark Syww9001 CountryTray 10.0Product Ordering InformationDatasheet