IXF1104
5.1.7Packet Buffer Dimensions
5.1.7.1TX and RX FIFO Operation
5.1.7.1.1TX FIFO
The IXF1104 TX FIFOs are implemented with 10 KB for each channel. This provides enough space for at least one maximum size (10 KB) packet
A transfer to MAC Threshold parameter, which is
5.1.7.1.2RX FIFO
The IXF1104 RX FIFOs are provisioned so that each port has its own 32 KB of memory space. This is enough memory to ensure that there is never an
The FIFOs automatically generate Pause control frames to halt the link partner when the High watermark is reached and to restart the link partner when the data stored in the FIFO falls below the
9.6 KB packets. The RX FIFO has a programmable transfer threshold that sets the threshold at which packets become “cut through” and starts transitioning to the SPI3 interface before the EOP is received. Packets sizes below this threshold are treated as “store and forward.” Once a packet size exceeds the RX FIFO transfer threshold, it can no longer be dropped by the RX FIFO even if it is marked to be dropped by the MAC.
5.1.8RMON Statistics Support
The IXF1104 supplies RMON statistics through the CPU interface. These statistics are available in the form of counter values that can be accessed at specific addresses in the register maps (Table 59 through Table 69). Once read, these counters automatically reset and begin counting from zero. A separate set of RMON statistics is available for each MAC device in the IXF1104.
Implementation of the RMON Statistics block is similar to the functionality provided by existing Intel switch and router products. This implementation allows the IXF1104 to provide all of the RMON Statistics group as defined by RFC2819. The IXF1104 supports the RMON RFC2819 Group 1 statistics counters. Table 25 notes the differences and additional statistics registers supported by the IXF1104 that are outside the scope of the RMON RFC2819 document.
Datasheet | 79 |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004