Intel IXF1104 manual 5.2.2.8.1Clock Rates, Datasheet

IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller

Figure 16. SPHY Connection for Two IXF1104 Ports (8-Bit Interface)

Network Processor	SPI3 Bus
	Intel® IXF1104
	Port 0
TFCLK	TFCLK
TENB[0]	TENB_0
TDAT[7:0][0]	TDAT[7:0]_0
TPRTY[0]	TPRTY_0
TSOP[0]	TSOP_0
TEOP[0]	TEOP_0
TERR[0]	TERR_0
DTPA[0]	DTPA_0
		Line-Side	Port 0
RFCLK	RFCLK	Interface
RENB[0]	RENB_0
RDAT[7:0][0]	RDAT[7:0]_0
RPRTY[0]	RPRTY_0
RVAL[0]	RVAL_0
RSOP[0]	RSOP_0
REOP[0]	REOP_0
RERR[0]	RERR_0
	SPI3
	Flow Control
PTPA	PTPA
TADR[1:0]	TADR[1:0]
	Port 1
TFCLK	TFCLK
TENB[1]	TENB_1
TDAT[7:0][1]	TDAT[7:0]_1
TPRTY[1]	TPRTY_1
TSOP[1]	TSOP_1
TEOP[1]	TEOP_1
TERR[1]	TERR_1
DTPA[1]	DTPA_1	Line-Side	Port 1
		Interface
	RFCLK
RFCLK
RENB[1]	RENB_1
RDAT[7:0][1]	RDAT[7:0]_1
RPRTY[1]	RPRTY_1
RVAL[1]	RVAL_1
RSOP[1]	RSOP_1
REOP[1]	REOP_1
RERR[1]	RERR_1

Transceiver

Transceiver

B0659-02

5.2.2.8.1Clock Rates

The TFCLK and RFCLK can be independent of each other in SPHY mode operation. TFCLK and RFCLK should be common to all the Network Processor devices. The IXF1104 requires an individual single clock source for the device transmit path and a single clock source for the device receive path.

The IXF1104 allows this interface to be overclocked so that all four IXF1104 ports can operate at 1 Gbps. This allows data transfer at data rates of up to 4.0 Gbps when operating at an overclocked frequency of 125 MHz.

Note: SPHY operates at a maximum frequency of 125Mhz.

Datasheet 89

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004