IXF1104
5.9.1Functional Description
5.9.1.1Read Access
Read access involves the following:
•Detect assertion of asynchronous Read control signal and latch address
•Generate internal Read strobe
•Drive valid data onto processor bus
•Assert asynchronous Ready signal for required length of time
Figure 31 shows the timing of the asynchronous interface for Read access.
Figure 31. Read Timing Diagram - Asynchronous Interface
uPx_ADD[12:0] |
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uPx_CsN |
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uPx_RdN
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uPx_Data[31:0] |
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TCDRH 
uPx_RdyN
TCDRD
5.9.1.2Write Access
Write process involves the following:
•Detect assertion of asynchronous Write control signal and latch address
•Detect
•Generate internal Write strobe
•Assert asynchronous Ready signal for required length of time
Figure 32 shows the timing of the asynchronous interface for Write accesses.
120 | Datasheet |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
