Intel IXF1104 5.3.1GMII Signal Multiplexing, 5.3.2GMII Interface Signal Definition, Datasheet

IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller

Figure 17. MAC GMII Interconnect

Intel® IXF1104 Media Access Controller

TXC_3:0 TXD[7:0]_0 TXD[7:0]_1 TXD[7:0]_2 TXD[7:0]_3 TX_EN_3:0 TX_ER_3:0

RXC_3:0 RXD[7:0]_0 RXD[7:0]_1 RXD[7:0]_2 RXD[7:0]_3 RX_EN_3:0 RX_ER_3:0

CRS_3:0 COL_3:0

TXC_3:0 TXD[7:0]_0 TXD[7:0]_1 TXD[7:0]_2 TXD[7:0]_3 TX_EN_3:0 TX_ER_3:0

RXC_3:0 RXD[7:0]_0 RXD[7:0]_1 RXD[7:0]_2 RXD[7:0]_3 RX_EN_3:0 RX_ER_3:0 CRS_3:0 COL_3:0

Quad PHY Device

B3203-01

5.3.1GMII Signal Multiplexing

The GMII balls are reassigned when using the RGMII mode or fiber mode. Table 16 “Line Side Interface Multiplexed Balls” on page 57 specifies the multiplexing of GMII balls in these modes. See Section 5.1.3, “Mixed-Mode Operation” on page 74 for proper configuration of the IXF1104 in GMII mode.

5.3.2GMII Interface Signal Definition

Table 26 “GMII Interface Signal Definitions” on page 94 provides the GMII interface signal definitions. For information on 1000BASE-T GMII transmit and receive timing diagrams and tables, please refer to Table 49 “GMII 1000BASE-T Transmit Signal Parameters” on page 141, Figure 38 “1000BASE-T Transmit Interface Timing” on page 141, Figure 39 “1000BASE-T Receive Interface Timing” on page 142, and Table 50 “GMII 1000BASE-T Receive Signal Parameters” on page 142

Datasheet 93

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004