IXF1104
Figure 12. MPHY Receive Logical Timing
TFCLK |
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RENB |
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RSX |
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RSOP |
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REOP |
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RERR |
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RMOD[1:0] |
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RDAT[31:0] | 0000 |
RPRTY
RVAL
Figure 13. MPHY
| SPI3 Bus |
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Network Processor | IXF1104 MPHY |
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| Mode | ||
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TFCLK | TFCLK | Transceiver | |
TENB | TENB_0 | ||
Port 0 | |||
TDAT[31:0] | TDAT[31:0] |
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TMOD[1:0] | TMOD[1:0] |
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TPRTY | TPRTY_0 |
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TSOP | TSOP_0 |
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TEOP | TEOP_0 | Transceiver | |
TERR | TERR_0 | Port 1 | |
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TSX | TSX |
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DTPA_0:3 | DTPA_0:3 |
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STPA | STPA | Transceiver | |
PTPA | PTPA | ||
Port 2 | |||
TADR[1:0] | TADR[1:0] | ||
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RFCLK | RFCLK |
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RENB | RENB_0 |
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RDAT[31:0] | RDAT[31:0] | Transceiver | |
RMOD[1:0] | RMOD[1:0] | Port 3 | |
RPRTY | RPRTY_0 |
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RVAL | RVAL_0 |
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RSOP | RSOP_0 |
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REOP | REOP_0 |
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RERR | RERR_0 |
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RSX | RSX |
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Datasheet |
| 85 |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004