IXF1104
Table 84. FC Enable ($ Port_Index + 0x12)
Bit | Name | Description | Type1 | Default | |
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Register Description: Indicates which flow control mode is used for the RX and TX MAC. | 0x00000007 | ||||
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31:3 | Reserved | Reserved | R | 0x00000000 | |
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| When TX HDFC is enabled |
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| only), the MAC generates deliberate collisions on |
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2 | TX HDFC | incoming packets when the RX FIFO occupancy | R/W | 1 | |
crosses the High Watermark (flow control). | |||||
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| 0 = Disable TX |
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| 1 = Enable TX |
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| 0 = Disable TX |
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| will not generate internally any flow control |
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| frames based on the RX FIFO watermarks or |
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| the Transmit Pause Control interface | R/W | 1 | |
1 | TX FDFC | 1 = Enable TX | |||
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| the MAC to send flow control frames to the |
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| link partner based on the RX FIFO |
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| programmable watermarks or the Transmit |
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| Pause Control interface] |
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| 0 = Disable RX |
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| will not respond to flow control frames sent to |
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| it by the link partner] |
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0 | RX FDFC | 1 = Enable RX | R/W | 1 | |
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| respond to flow control frames sent by the link |
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| partner and will stop packet transmission for |
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| the time specified in the flow control frame] |
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1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
Table 85. FC Back Pressure Length ($ Port_Index + 0x13)
Name | Description | Address | Type1 | Default | |
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| This register sets number the byte cycles |
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| for which the collision has to be applied. |
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| The |
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FC Back Pressure | bytes, which applies to the minimum | Port Add + |
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length/duration of back pressure in half- | R/W | 0x0000000C | |||
Length | 0x13 | ||||
duplex mode. Flow control in the receive |
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| path is executed by deliberately colliding |
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| the incoming packets in |
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| Register bits 5:0 are used alone. |
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1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
Datasheet | 167 |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004