Intel 80200, Processor Branch Target Buffer

Developer’s Manual March, 2003 5-1

Branch Target Buffer

Intel® 80200 processor based on Intel® XScale™ microarchitecture (compliant with the ARM*

Architecture V5TE) uses dynamic branch prediction to reduce the penalties associated with

changing the flow of program execution. The Intel® 80200 processor features a branch target

buffer that provides the instruction cache with the target address of branch type instructions. The

branch target buffer is implemented as a 128-entry, direct mapped cache.

This chapter is primarily for those optimizing their code for performance. An understanding of the

branch target buffer is needed in this case so that code can be scheduled to best utilize the

performance benefits of the branch target buffer.

The BTB stores the history of branches that have executed along with their targets. Figure5-1

shows an entry in the BTB, where the tag is the instruction address of a previously executed branch

and the data contains the target address of the previously executed branch along with two bits of

history information.

The BTB takes the current instruction address and checks to see if this address is a branch that was

previously seen. It uses bits [8:2] of the current address to read out the tag and then compares this

tag to bits [31:9,1] of the current instruction address. If the current instruction address matches the

tag in the cache and the history bits indicate that this branch is usually taken in the past, the BTB

uses the data (target address) as the next instruction address to send to the instruction cache.

Bit[1] of the instruction address is included in the tag comparison in order to support Thumb*

execution. This organization means that two consecutive Thumb branch (B) instructions, with

instruction address bits[8:2] the same, contends for the same BTB entry. Thumb also requires

31bits for the branch target address. In ARM* mode, bit[1] is zero.

The history bits represent four possible prediction states for a branch entry in the BTB. Figure5-2,

“Branch History” on page 5-2 shows these states along with the possible transitions. The initial

state for branches stored in the BTB is Weakly-Taken (WT). Every time a branch that exists in the

BTB is executed, the history bits are updated to reflect the latest outcome of the branch, either

taken or not-taken.

Chapter14, “Performance Considerations” describes which instructions are dynamically predicted

by the BTB and the performance penalty for mispredicting a branch.

The BTB does not have to be managed explicitly by software; it is disabled by default after reset

and is invalidated when the instruction cache is invalidated.

Figure 5-1. BTB Entry

Branch Address[31:9,1] Target Address[31:1] History

DATA

TAG

Bits[1:0]