iv March, 2003 Developer’s Manual
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
3.2.2.1 Page (P) Attribute Bit............................................. ...................................2
3.2.2.2 Cacheable (C), Bufferable (B), and eXtension (X) Bits ............................ 2
3.2.2.3 Instruction Cache...................................................................................... 2
3.2.2.4 Data Cache and Write Buffer........................................................... .........3
3.2.2.5 Details on Data Cache and Write Buffer Behavior ................................... 4
3.2.2.6 Memory Operation Ordering........................................ .............................4
3.2.3 Exceptions............................ ....................................................................... ................ 4
3.3 Interaction of the MMU, Instruction Cache, and Data Cache ....................................................... 5
3.4 Control............................................. ................................................................ ............................. 6
3.4.1 Invalidate (Flush) Operation ........................................................................................ 6
3.4.2 Enabling/Disabling.......................................... ............................................................. 6
3.4.3 Locking Entries............................ ................................................................................7
3.4.4 Round-Robin Replacement Algorithm ......................................................................... 9
4 Instruction Cache.....................................................................................1
4.1 Overview.................................................................................................... ...................................1
4.2 Operation......................................................................... ............................................................. 2
4.2.1 Operation When Instruction Cache is Enabled...................................... ......................2
4.2.2 Operation When The Instruction Cache Is Disabled.................................................... 2
4.2.3 Fetch Policy.......................... ....................................................................................... 3
4.2.4 Round-Robin Replacement Algorithm ......................................................................... 3
4.2.5 Parity Protection ..........................................................................................................4
4.2.6 Instruction Fetch Latency............................................................................................. 5
4.2.7 Instruction Cache Coherency ...................................................................................... 5
4.3 Instruction Cache Control................ ............................................................................................. 6
4.3.1 Instruction Cache State at RESET .............................................................................. 6
4.3.2 Enabling/Disabling.......................................... ............................................................. 6
4.3.3 Invalidating the Instruction Cache............................................................................. ...7
4.3.4 Locking Instructions in the Instruction Cache ..............................................................8
4.3.5 Unlocking Instructions in the Instruction Cache.............................. .............................9
5 Branch Target Buffer ...............................................................................1
5.1 Branch Target Buffer (BTB) Operation.. .......................................................................................1
5.1.1 Reset.......... ....................................................................... .......................................... 2
5.1.2 Update Policy............................................................................................................... 2
5.2 BTB Control........................................... ....................................................................................... 3
5.2.1 Disabling/Enabling.................................... ................................................................... 3
5.2.2 Invalidation.......................................................................................................... .........3
6 Data Cache................................................................................................1
6.1 Overviews.................................................................. ................................................................... 1
6.1.1 Data Cache Overview.................................................................................. ................1
6.1.2 Mini-Data Cache Overview................................... .......................................................3
6.1.3 Write Buffer and Fill Buffer Overview.................................................................. .........4
6.2 Data Cache and Mini-Data Cache Operation ............................................................................... 5
6.2.1 Operation When Caching is Enabled........................................................................ ...5
6.2.2 Operation When Data Caching is Disabled ................................................................. 5
6.2.3 Cache Policies...................................................... .......................................................5
6.2.3.1 Cacheability........................... ................................................................ ... 5
6.2.3.2 Read Miss Policy......................... .............................................................6