viii March, 2003 Developer’s Manual
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
13.11.6.4 DBG.V ...................................................... .............................................. 25
13.11.6.5 DBG.RX....................................................................... ........................... 25
13.11.6.6 DBG.D............... ....................................................................... .............. 25
13.11.6.7 DBG.FLUSH...................................... ..................................................... 25
13.11.7 Debug JTAG Data Register Reset Values................................................................. 25
13.12 Trace Buffer..................................................................... ...........................................................26
13.12.1 Trace Buffer CP Registers..................................................................... ....................26
13.12.1.1 Checkpoint Registers ............................................................................. 26
13.12.1.2 Trace Buffer Register (TBREG).............................................................. 27
13.13 Trace Buffer Entries................................................................................... .................................28
13.13.1 Message Byte.............................................................. ..............................................28
13.13.1.1 Exception Message Byte............. ...........................................................29
13.13.1.2 Non-exception Message Byte................................................................. 30
13.13.1.3 Address Bytes ........................................................................................ 31
13.13.2 Trace Buffer Usage.................................................................................................... 32
13.14 Downloading Code in the ICache.............................. .................................................................34
13.14.1 LDIC JTAG Command........................................................................... ....................34
13.14.2 LDIC JTAG Data Register ......................................................................................... 35
13.14.3 LDIC Cache Functions............................................................................................... 36
13.14.4 Loading IC During Reset ........................................................................................... 38
13.14.4.1 Loading IC During Cold Reset for Debug ...............................................39
13.14.4.2 Loading IC During a Warm Reset for Debug...................... ....................41
13.14.5 Dynamically Loading IC After Reset..................... .....................................................43
13.14.5.1 Dynamic Code Download Synchronization ............................................ 45
13.14.6 Mini Instruction Cache Overview ............................................................................... 46
13.15 Halt Mode Software Protocol........................................... ...........................................................47
13.15.1 Starting a Debug Session.................................................. ........................................47
13.15.1.1 Setting up Override Vector Tables ......................................................... 47
13.15.1.2 Placing the Handler in Memory .............................................................. 48
13.15.2 Implementing a Debug Handler................................................ .................................49
13.15.2.1 Debug Handler Entry................... ...........................................................49
13.15.2.2 Debug Handler Restrictions............................................................. .......49
13.15.2.3 Dynamic Debug Handler ........................................................................ 50
13.15.2.4 High-Speed Download........................................................................... .52
13.15.3 Ending a Debug Session ........................................................................................... 53
13.16 Software Debug Notes/Errata................................................................................. ....................54
14 Performance Considerations..................................................................114.1 Interrupt Latency........................................................................................ ...................................1
14.2 Branch Prediction ......................................................................................................................... 2
14.3 Addressing Modes........................................................... .............................................................2
14.4 Instruction Latencies.................................................................................. ...................................3
14.4.1 Performance Terms........................................ .............................................................3
14.4.2 Branch Instruction Timings... ....................................................................................... 4
14.4.3 Data Processing Instruction Timings ...........................................................................5
14.4.4 Multiply Instruction Timings ......................................................................................... 6
14.4.5 Saturated Arithmetic Instructions....................................... ..........................................8
14.4.6 Status Register Access Instructions ............................................................................ 8
14.4.7 Load/Store Instructions................................................................... .............................8
14.4.8 Semaphore Instructions.................................................................. .............................9
14.4.9 Coprocessor Instructions................................ .............................................................9