Intel 80200, Processor 6.1.2 Mini-Data Cache Overview

Developer’s Manual March, 2003 6-3
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
Data Cache
6.1.2 Mini-Data Cache Overview
The mini-data cache is a 2-Kbyte, 2-way set associative cache; this means there are 32sets with
each set containing 2ways. Each way of a set contains 32 bytes (one cache line) and one valid bit.
There also exist 2dirty bits for every line, one for the lower 16 bytes and the other one for the
upper 16bytes. When a store hits the cache the dirty bit associated with it is set. The replacement
policy is a round-robin algorithm.
Figure6-2, “Mini-Data Cache Organization” on page 6-3 shows the cache organization and how
the data address is used to access the cache.
The mini-data cache is virtually addressed and virtually tagged and supports the same caching
policies as the data cache. However, lines can’t be locked into the mini-data cache.
Figure 6-2. Mini-Data Cache Organization
way 0
way 1 32 bytes (cache line)
Set 1
way 0
way 1 32 bytes (cache line)
Set Index
Set 0
Tag
Data Word
(4 bytes to Destination Register)
Data Address (Virtual)
31 109 54 210
Tag Set I ndex Word Byte
Word Select
This example
shows Set 0
being selected by way 0
way 1 32 bytes (cache line)
Set 31
Byte Alignment
Sign Extension
Byte Select